| Integral memory buffer and serial presence detect capability for fully-buffered memory modules K Bains, R Ellis, C Freeman, J Halbert, M Williams US Patent App. 10/746,948, 2005 | 218 | 2005 |
| Co-architecting controllers and DRAM to enhance DRAM process scaling U Kang, HS Yu, C Park, H Zheng, J Halbert, K Bains, S Jang, JS Choi The memory forum 14, 2014 | 214 | 2014 |
| Row hammer refresh command K Bains, J Halbert, C Mozak, T Schoenborn, Z Greenfield US Patent 9,117,544, 2015 | 193 | 2015 |
| Memory device having error checking and correction RM Ellis, KS Bains, CB Freeman, JB Halbert US Patent 7,386,765, 2008 | 179 | 2008 |
| Distributed row hammer tracking KS Bains, JB Halbert US Patent 9,299,400, 2016 | 177 | 2016 |
| Row hammer refresh command KS Bains, JB Halbert, CP Mozak, TZ Schoenborn, Z Greenfield US Patent 9,236,110, 2016 | 163 | 2016 |
| Row hammer monitoring based on stored row hammer threshold value KS Bains, JB Halbert US Patent 9,032,141, 2015 | 158 | 2015 |
| Row hammer monitoring based on stored row hammer threshold value KS Bains, JB Halbert US Patent 9,384,821, 2016 | 156 | 2016 |
| Row hammer condition monitoring Z Greenfield, KS Bains, TZ Schoenborn, CP Mozak, JB Halbert US Patent 8,938,573, 2015 | 148 | 2015 |
| Reliability, availability, and serviceability in a memory device KS Bains US Patent 8,806,298, 2014 | 126 | 2014 |
| Method, apparatus and system for providing a memory refresh KS Bains, JB Halbert, S Sah, Z Greenfield US Patent 9,030,903, 2015 | 120 | 2015 |
| Method, apparatus and system for responding to a row hammer event JB Halbert, KS Bains US Patent 9,286,964, 2016 | 116 | 2016 |
| Memory buffer device integrating refresh logic RM Ellis, KS Bains, CB Freeman, JB Halbert, NS Khandekar, ... US Patent 7,353,329, 2008 | 114 | 2008 |
| Method and apparatus to calibrate DRAM on resistance (Ron) and on-die termination (ODT) values over process, voltage and temperature (PVT) variations KS Bains, N Dour, H Fahmy, G Vergis, CE Cox US Patent 7,432,731, 2008 | 107 | 2008 |
| Method and system for error management in a memory device KS Bains, DJ Zimmerman, DW Brzezinski, M Williams, JB Halbert US Patent 8,862,973, 2014 | 106 | 2014 |
| Command controlling different operations in different chips KS Bains US Patent 7,433,992, 2008 | 100 | 2008 |
| Method and apparatus to counter mismatched burst lengths KS Bains, JB Halbert, RB Osborne US Patent 7,281,079, 2007 | 99 | 2007 |
| Memory device specific self refresh entry and exit G Vergis, KS Bains, JA McCall, MK Nachimuthu, MJ Kumar US Patent App. 14/998,058, 2016 | 95 | 2016 |
| Mapping a physical address differently to different memory devices in a group KS Bains, S Sah, JH Crawford, BS Morris US Patent 9,934,143, 2018 | 91 | 2018 |
| Method and apparatus for providing concurrent access by a plurality of agents to a shared memory M Muthal, NV Shah, K Bains US Patent 5,815,167, 1998 | 91 | 1998 |
