| A ferroelectric semiconductor field-effect transistor M Si, AK Saha, S Gao, G Qiu, J Qin, Y Duan, J Jian, C Niu, H Wang, W Wu, ... Nature Electronics 2 (12), 580-586, 2019 | 508 | 2019 |
| A steep-slope transistor based on abrupt electronic phase transition N Shukla, AV Thathachary, A Agrawal, H Paik, A Aziz, DG Schlom, ... Nature communications 6 (1), 7812, 2015 | 395 | 2015 |
| Physics-based circuit-compatible SPICE model for ferroelectric transistors A Aziz, S Ghosh, S Datta, SK Gupta IEEE Electron Device Letters 37 (6), 805-808, 2016 | 199 | 2016 |
| KNACK: A hybrid spin-charge mixed-mode simulator for evaluating different genres of spin-transfer torque MRAM bit-cells X Fong, SK Gupta, NN Mojumder, SH Choday, C Augustine, K Roy 2011 International Conference on Simulation of Semiconductor Processes and …, 2011 | 184 | 2011 |
| Pathways to efficient neuromorphic computing with non-volatile memory technologies I Chakraborty, A Jaiswal, AK Saha, SK Gupta, K Roy Applied Physics Reviews 7 (2), 2020 | 160 | 2020 |
| Nonvolatile memory design based on ferroelectric FETs S George, K Ma, A Aziz, X Li, A Khan, S Salahuddin, MF Chang, S Datta, ... Proceedings of the 53rd Annual Design Automation Conference, 1-6, 2016 | 138 | 2016 |
| A three-terminal dual-pillar STT-MRAM for high-performance robust memory applications NN Mojumder, SK Gupta, SH Choday, DE Nikonov, K Roy IEEE transactions on electron devices 58 (5), 1508-1516, 2011 | 132 | 2011 |
| Future cache design using STT MRAMs for improved energy efficiency: Devices, circuits and architecture SP Park, S Gupta, N Mojumder, A Raghunathan, K Roy Proceedings of the 49th Annual Design Automation Conference, 492-497, 2012 | 130 | 2012 |
| Asymmetric drain spacer extension (ADSE) FinFETs for low-power and robust SRAMs A Goel, SK Gupta, K Roy IEEE Transactions on Electron Devices 58 (2), 296-308, 2010 | 129 | 2010 |
| Device-circuit analysis of ferroelectric FETs for low-power logic S Gupta, M Steiner, A Aziz, V Narayanan, S Datta, SK Gupta IEEE Transactions on Electron Devices 64 (8), 3092-3100, 2017 | 118 | 2017 |
| Ferroelectric transistor model based on self-consistent solution of 2D Poisson's, non-equilibrium Green's function and multi-domain Landau Khalatnikov equations AK Saha, P Sharma, I Dabo, S Datta, SK Gupta 2017 IEEE International Electron Devices Meeting (IEDM), 13.5. 1-13.5. 4, 2017 | 106 | 2017 |
| Layout-aware optimization of STT MRAMs SK Gupta, SP Park, NN Mojumder, K Roy 2012 Design, Automation & Test in Europe Conference & Exhibition (DATE …, 2012 | 106 | 2012 |
| “Negative capacitance” in resistor-ferroelectric and ferroelectric-dielectric networks: apparent or intrinsic? AK Saha, S Datta, SK Gupta Journal of Applied Physics 123 (10), 2018 | 102 | 2018 |
| Enabling energy-efficient nonvolatile computing with negative capacitance FET X Li, J Sampson, A Khan, K Ma, S George, A Aziz, SK Gupta, ... IEEE Transactions on Electron Devices 64 (8), 3452-3458, 2017 | 97 | 2017 |
| Write-optimized reliable design of STT MRAM Y Kim, SK Gupta, SP Park, G Panagopoulos, K Roy Proceedings of the 2012 ACM/IEEE international symposium on Low power …, 2012 | 95 | 2012 |
| Phase field modeling of domain dynamics and polarization accumulation in ferroelectric HZO AK Saha, K Ni, S Dutta, S Datta, S Gupta Applied Physics Letters 114 (20), 2019 | 94 | 2019 |
| Computing with ferroelectric FETs: Devices, models, systems, and applications A Aziz, ET Breyer, A Chen, X Chen, S Datta, SK Gupta, M Hoffmann, ... 2018 Design, Automation & Test in Europe Conference & Exhibition (DATE …, 2018 | 90 | 2018 |
| Impact of total and partial dipole switching on the switching slope of gate-last negative capacitance FETs with ferroelectric hafnium zirconium oxide gate stack P Sharma, K Tapily, AK Saha, J Zhang, A Shaughnessy, A Aziz, ... 2017 Symposium on VLSI Technology, T154-T155, 2017 | 90 | 2017 |
| Digital computation in subthreshold region for ultralow-power operation: A device–circuit–architecture codesign perspective SK Gupta, A Raychowdhury, K Roy Proceedings of the IEEE 98 (2), 160-190, 2010 | 90 | 2010 |
| The design and hardware implementation of a low-power real-time seizure detection algorithm S Raghunathan, SK Gupta, MP Ward, RM Worth, K Roy, PP Irazoqui Journal of neural engineering 6 (5), 056005, 2009 | 90 | 2009 |
Suman DattaJoseph M. Pettit Chair Professorبريد إلكتروني تم التحقق منه على gatech.edu
