A 4.68 Gb/s belief propagation polar decoder with bit-splitting register file YS Park, Y Tao, S Sun, Z Zhang 2014 IEEE Symposium on VLSI Circuits, 1-2, 2014 | 118 | 2014 |
A configurable successive-cancellation list polar decoder using split-tree architecture Y Tao, SG Cho, Z Zhang IEEE Journal of Solid-State Circuits 56 (2), 612-623, 2021 | 49 | 2021 |
A fully parallel nonbinary LDPC decoder with fine-grained dynamic clock gating YS Park, Y Tao, Z Zhang IEEE Journal of Solid-State Circuits 50 (2), 464-475, 2014 | 48 | 2014 |
MOD-Net: A machine learning approach via model-operator-data network for solving PDEs L Zhang, T Luo, Y Zhang, ZQJ Xu, Z Ma arXiv preprint arXiv:2107.03673, 2021 | 42 | 2021 |
High-throughput architecture and implementation of regular (2, dc) nonbinary LDPC decoders Y Tao, YS Park, Z Zhang 2013 IEEE International Symposium on Circuits and Systems, 2625-2628, 2013 | 23 | 2013 |
Part-based structured representation learning for person re-identification Y Li, H Yao, T Zhang, C Xu ACM Transactions on Multimedia Computing, Communications, and Applications …, 2020 | 22 | 2020 |
A 1.15 Gb/s fully parallel nonbinary LDPC decoder with fine-grained dynamic clock gating YS Park, Y Tao, Z Zhang IEEE International Solid-State Circuits Conference (ISSCC), 422-423, 2013 | 22 | 2013 |
Integrated memristor network for physiological signal processing L Cai, L Yu, W Yue, Y Zhu, Z Yang, Y Li, Y Tao*, Y Yang* Advanced Electronic Materials 9 (6), 2300021, 2023 | 19 | 2023 |
LDPC post-processor architecture and method for low error floor conditions Y Tao, J Kwong US Patent 9,793,923, 2017 | 17 | 2017 |
Molecular insights into enhanced nitrogen removal induced by trace fluoroquinolone antibiotics in an anammox system X Qiao, C Fu, Y Chen, F Fang, Y Zhang, L Ding, K Yang, B Pan, N Xu, ... Bioresource Technology 374, 128784, 2023 | 15 | 2023 |
High-Throughput Split-Tree Architecture for Nonbinary SCL Polar Decoder Y Tao, C Choi 2022 IEEE International Symposium on Circuits and Systems, 2057-2061, 2022 | 13 | 2022 |
Algorithm-architecture co-design for domain-specific accelerators in communication and artificial intelligence Y Tao University of Michigan Ann Arbor, 2022 | 13 | 2022 |
VO2 memristor-based frequency converter with in-situ synthesize and mix for wireless internet-of-things C Liu, PJ Tiw, T Zhang, Y Wang, L Cai, R Yuan, Z Pan, W Yue, Y Tao*, ... Nature Communications 15 (1), 1523, 2024 | 9 | 2024 |
DNC-aided SCL-flip decoding of polar codes Y Tao, Z Zhang 2021 IEEE Global Communications Conference (GLOBECOM), 01-06, 2021 | 9 | 2021 |
A scalable universal Ising machine based on interaction-centric storage and compute-in-memory W Yue, T Zhang, Z Jing, K Wu, Y Yang, Z Yang, Y Wu, W Bu, K Zheng, ... Nature Electronics (2024), 2520-1131, 2024 | 8 | 2024 |
HiMA: A Fast and Scalable History-based Memory Access Engine for Differentiable Neural Computer Y Tao, Z Zhang 54th IEEE/ACM International Symposium on Microarchitecture (MICRO), 845-856, 2021 | 8 | 2021 |
Efficient in situ error detection enabling diverse path coverage CH Chen, Y Tao, Z Zhang 2013 IEEE International Symposium on Circuits and Systems, 773-776, 2013 | 7 | 2013 |
Neural Architecture Search with In‐Memory Multiply–Accumulate and In‐Memory Rank Based on Coating Layer Optimized C‐Doped Ge2Sb2Te5 Phase Change … L Yan, Q Wu, X Li, C Xie, X Zhou, Y Li, D Shi, L Yu, T Zhang, Y Tao, B Yan, ... Advanced Functional Materials 34 (15), 2300458, 2024 | 6 | 2024 |
Arvon: A Heterogeneous System-in-Package Integrating FPGA and DSP Chiplets for Versatile Workload Acceleration W Tang, SG Cho, TT Hoang, J Botimer, WQ Zhu, CC Chang, CH Lu, J Zhu, ... IEEE Journal of Solid-State Circuits (JSSC), 1 - 11, 2023 | 6 | 2023 |
Fast and scalable memristive in-memory sorting with column-skipping algorithm L Yu, Z Jing, Y Yang, Y Tao 2022 IEEE International Symposium on Circuits and Systems, 590-594, 2022 | 6 | 2022 |