| Bypass and insertion algorithms for exclusive last-level caches J Gaur, M Chaudhuri, S Subramoney Proceedings of the 38th annual international symposium on Computer …, 2011 | 151 | 2011 |
| Introducing hierarchy-awareness in replacement and bypass algorithms for last-level caches M Chaudhuri, J Gaur, N Bashyam, S Subramoney, J Nuzman Proceedings of the 21st international conference on Parallel architectures …, 2012 | 95 | 2012 |
| Density tradeoffs of non-volatile memory as a replacement for SRAM based last level cache K Korgaonkar, I Bhati, H Liu, J Gaur, S Manipatruni, S Subramoney, ... 2018 ACM/IEEE 45th Annual International Symposium on Computer Architecture …, 2018 | 73 | 2018 |
| Using data pattern to mark cache lines as invalid J Gaur, S Majumder, Z Greenfield, I Diamand US Patent 10,176,099, 2019 | 54 | 2019 |
| Criticality aware tiered cache hierarchy: A fundamental relook at multi-level cache hierarchies AV Nori, J Gaur, S Rai, S Subramoney, H Wang 2018 ACM/IEEE 45th Annual International Symposium on Computer Architecture …, 2018 | 43 | 2018 |
| Cryptographic capability computing M LeMay, J Rakshit, S Deutsch, DM Durham, S Ghosh, A Nori, J Gaur, ... MICRO-54: 54th Annual IEEE/ACM International Symposium on Microarchitecture …, 2021 | 41 | 2021 |
| Base-victim compression: An opportunistic cache compression architecture J Gaur, AR Alameldeen, S Subramoney ACM SIGARCH Computer Architecture News 44 (3), 317-328, 2016 | 35 | 2016 |
| Cryptographic computing engine for memory load and store units of a microarchitecture pipeline DM Durham, M LeMay, ME Kounavis, S Ghosh, S Deutsch, AV Nori, ... US Patent 11,575,504, 2023 | 32 | 2023 |
| Stream floating: Enabling proactive and decentralized cache optimizations Z Wang, J Weng, J Lowe-Power, J Gaur, T Nowatzki 2021 IEEE International Symposium on High-Performance Computer Architecture …, 2021 | 31 | 2021 |
| Efficient management of last-level caches in graphics processors for 3d scene rendering workloads J Gaur, R Srinivasan, S Subramoney, M Chaudhuri Proceedings of the 46th Annual IEEE/ACM International Symposium on …, 2013 | 31 | 2013 |
| Efficient hardware-based extraction of program instructions for critical paths J Gaur, P Roy, S Subramoney, H Wang, R Singhal US Patent 10,496,413, 2019 | 27 | 2019 |
| Post-silicon cpu adaptation made practical using machine learning SJ Tarsa, RBR Chowdhury, J Sebot, G Chinya, J Gaur, ... Proceedings of the 46th International Symposium on Computer Architecture, 14-26, 2019 | 27 | 2019 |
| Near-optimal access partitioning for memory hierarchies with multiple heterogeneous bandwidth sources J Gaur, M Chaudhuri, P Ramachandran, S Subramoney 2017 IEEE International Symposium on High Performance Computer Architecture …, 2017 | 22 | 2017 |
| Focused Value Prediction: Concepts, techniques and implementations presented in this paper are subject matter of pending patent applications, which have been filed by Intel … S Bandishte, J Gaur, Z Sperber, L Rappoport, A Yoaz, S Subramoney 2020 ACM/IEEE 47th Annual International Symposium on Computer Architecture …, 2020 | 17 | 2020 |
| Bypass and insertion algorithms for exclusive last-level caches J Gaur, M Chaudhuri, S Subramoney US Patent 8,667,222, 2014 | 17 | 2014 |
| Hierarchy-aware Replacement Policy J Gaur, M Chaudhuri, S Subramoney, N Bashyam, J Nuzman US Patent App. 13/722,607, 2013 | 16 | 2013 |
| Leveraging semi-formal and sequential equivalence techniques for multimedia SoC performance validation L Bhatia, J Gaur, P Tiwari, RS Mitra, SH Matange Proceedings of the 44th annual Design Automation Conference, 69-74, 2007 | 15 | 2007 |
| Sealing device and positioning device using the same T Nakamura, N Saji US Patent App. 10/013,352, 2002 | 14* | 2002 |
| Write congestion aware bypass for non-volatile memory, last level cache (LLC) dropping from write queue responsive to write queue being full and read queue threshold wherein … IS Bhati, H Liu, J Gaur, K Korgaonkar, S Manipatruni, S Subramoney, ... US Patent 10,331,582, 2019 | 13 | 2019 |
| Criticality aware tiered cache hierarchy: a fundamental relook at multi-level cache hierarchies. In 2018 ACM/IEEE 45th Annual International Symposium on Computer Architecture … AV Nori, J Gaur, S Rai, S Subramoney, H Wang IEEE, 96ś109, 2018 | 12 | 2018 |