| Lowering the error floor of LDPC codes using multi-step quantization S Tolouei, AH Banihashemi IEEE communications letters 18 (1), 86-89, 2013 | 16 | 2013 |
| Fast and accurate error floor estimation of quantized iterative decoders for variable-regular LDPC codes S Tolouei, AH Banihashemi IEEE communications letters 18 (8), 1283-1286, 2014 | 15 | 2014 |
| Successive relaxation for decoding of LDPC codes H Xiao, S Tolouei, AH Banihashemi 2008 24th Biennial Symposium on Communications, 107-110, 2008 | 11 | 2008 |
| FPGA implementation of variants of min-sum algorithm S Tolouei, AH Banihashemi 2008 24th Biennial Symposium on Communications, 80-83, 2008 | 4 | 2008 |
| High Speed Low Error Floor Hardware Implementation and Fast and Accurate Error Floor Estimation of LDPC Decoders S Tolouei Carleton University, 2014 | 2 | 2014 |
| Design and FPGA implementation of Min-Sum algorithm and its variants S Tolouei Carleton University, 2008 | 1 | 2008 |
