Neural cache: Bit-serial in-cache acceleration of deep neural networks C Eckert, X Wang, J Wang, A Subramaniyan, R Iyer, D Sylvester, ...
2018 ACM/IEEE 45Th annual international symposium on computer architecture …, 2018
482 2018 A 28-nm compute SRAM with bit-serial logic/arithmetic operations for programmable in-memory vector computing J Wang, X Wang, C Eckert, A Subramaniyan, R Das, D Blaauw, ...
IEEE Journal of Solid-State Circuits 55 (1), 76-86, 2019
190 2019 14.7 a 288µw programmable deep-learning processor with 270kb on-chip weight storage using non-uniform memory hierarchy for mobile intelligence S Bang, J Wang, Z Li, C Gao, Y Kim, Q Dong, YP Chen, L Fick, X Sun, ...
2017 IEEE International Solid-State Circuits Conference (ISSCC), 250-251, 2017
136 2017 14.2 A compute SRAM with bit-serial integer/floating-point operations for programmable in-memory vector acceleration J Wang, X Wang, C Eckert, A Subramaniyan, R Das, D Blaauw, ...
2019 IEEE International Solid-State Circuits Conference-(ISSCC), 224-226, 2019
130 2019 Recryptor: A reconfigurable cryptographic cortex-M0 processor with in-memory and near-memory computing for IoT security Y Zhang, L Xu, Q Dong, J Wang, D Blaauw, D Sylvester
IEEE Journal of Solid-State Circuits 53 (4), 995-1005, 2018
122 2018 A dual-slope capacitance-to-digital converter integrated in an implantable pressure-sensing system S Oh, Y Lee, J Wang, Z Foo, Y Kim, W Jung, Z Li, D Blaauw, D Sylvester
IEEE Journal of solid-state circuits 50 (7), 1581-1591, 2015
118 2015 Cache automaton A Subramaniyan, J Wang, ERM Balasubramanian, D Blaauw, D Sylvester, ...
Proceedings of the 50th Annual IEEE/ACM International Symposium on …, 2017
89 2017 A 0.04MM3 16NW Wireless and Batteryless Sensor System with Integrated Cortex-M0+ Processor and Optical Communication for Cellular Temperature Measurement X Wu, I Lee, Q Dong, K Yang, D Kim, J Wang, Y Peng, Y Zhang, ...
2018 IEEE Symposium on VLSI Circuits, 191-192, 2018
59 2018 A fixed-point neural network architecture for speech applications on resource constrained hardware M Shah, S Arunachalam, J Wang, D Blaauw, D Sylvester, HS Kim, J Seo, ...
Journal of Signal Processing Systems 90, 727-741, 2018
34 2018 A fixed-point neural network for keyword detection on resource constrained hardware M Shah, J Wang, D Blaauw, D Sylvester, HS Kim, C Chakrabarti
2015 IEEE Workshop on Signal Processing Systems (SiPS), 1-6, 2015
31 2015 A 1920 Z Li, J Wang, D Sylvester, D Blaauw, HS Kim
IEEE Journal of Solid-State Circuits 54 (4), 1048-1058, 2019
28 2019 17.3 a reconfigurable dual-port memory with error detection and correction in 28nm fdsoi M Khayatzadeh, M Saligane, J Wang, M Alioto, D Blaauw, D Sylvester
2016 IEEE International Solid-State Circuits Conference (ISSCC), 310-312, 2016
26 2016 11.2 A 1Mb embedded NOR flash memory with 39µW program power for mm-scale high-temperature sensor nodes Q Dong, Y Kim, I Lee, M Choi, Z Li, J Wang, K Yang, YP Chen, J Dong, ...
2017 IEEE International Solid-State Circuits Conference (ISSCC), 198-199, 2017
23 2017 An ultra-low-power image signal processor for hierarchical image recognition with deep neural networks H An, S Schiferl, S Venkatesan, T Wesley, Q Zhang, J Wang, KD Choo, ...
IEEE Journal of Solid-State Circuits 56 (4), 1071-1081, 2020
18 2020 A 40-nm ultra-low leakage voltage-stacked SRAM for intelligent IoT sensors J Wang, H An, Q Zhang, HS Kim, D Blaauw, D Sylvester
IEEE Solid-State Circuits Letters 4, 14-17, 2020
18 2020 1.03 pW/b ultra-low leakage voltage-stacked SRAM for intelligent edge processors J Wang, H An, Q Zhang, HS Kim, D Blaauw, D Sylvester
2020 IEEE Symposium on VLSI Circuits, 1-2, 2020
14 2020 A 170μW Image Signal Processor Enabling Hierarchical Image Recognition for Intelligence at the Edge H An, S Venkatesan, S Schiferl, T Wesley, Q Zhang, J Wang, K Choo, ...
2020 IEEE Symposium on VLSI Circuits, 1-2, 2020
12 2020 Reconfigurable self-timed regenerators for wide-range voltage scaled interconnect J Wang, N Pinckney, D Blaauw, D Sylvester
2015 IEEE Asian Solid-State Circuits Conference (A-SSCC), 1-4, 2015
7 2015 A1920× 1080 25FPS, 2.4 TOPS/W Unified Optical Flow and Depth 6D Vision Processor for Energy-Efficient, Low Power Autonomous Navigation Z Li, J Wang, D Sylvester, D Blaauw, HS Kim
2018 IEEE Symposium on VLSI Circuits, 135-136, 2018
6 2018 Cache automaton: Repurposing caches for automata processing A Subramaniyan, J Wang, ERM Balasubramanian, D Blaauw, D Sylvester, ...
2017 26th International Conference on Parallel Architectures and Compilation …, 2017
4 2017 
David BlaauwProfessor of Electrical Engineering and Computer Science, University of Michiganبريد إلكتروني تم التحقق منه على umich.edu