| Impact of work function engineering on strained silicon based double gated junction-less transistor TR Pokhrel, A Majumder Silicon 14 (15), 10061-10069, 2022 | 9 | 2022 |
| A variation resilient keeper design for high performance domino logic applications J Kandpal, TR Pokhrel, S Saini, A Majumder Integration 88, 1-9, 2023 | 4 | 2023 |
| Study of Power-Delay Improved Logic Circuit using Strained Silicon DG-JLT with Variable Gate Work Function TR Pokhrel, A Majumder 2022 IEEE Region 10 Symposium (TENSYMP), 1-5, 2022 | 1 | 2022 |
| Exploring Dual threshold in a Double Gated TIG JLT for a logic Application TR Pokhrel, A Majumder 2024 8th IEEE Electron Devices Technology & Manufacturing Conference (EDTM), 1-3, 2024 | | 2024 |
| Double Gate JLT Based New TIGFET for Dynamic C2MOS Application TR Pokhrel, A Majumder 2023 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS), 246-250, 2023 | | 2023 |
| Configuring a Hybrid Full Adder Using Strained-Si Channel DG JLT with Work Function Modulation TR Pokhrel, J Kandpal, A Majumder Silicon 15 (10), 4513-4519, 2023 | | 2023 |
| Junctionless Transistors TR Pokhrel, A Majumder Nanoscale Semiconductors: Materials, Devices and Circuits, 213, 2022 | | 2022 |
| Junctionless Transistors: Evolution and Prospects TR Pokhrel, A Majumder Nanoscale Semiconductors, 213-236, 2022 | | 2022 |
| Design and Analysis of Differentially Graded Double Gated Junctionless Transistors T Pokhrel, RS Dhar 2019 Second International Conference on Advanced Computational and …, 2019 | | 2019 |
Alak MajumderAssistant Professor, NIT Arunachal Pradesh, Indiaبريد إلكتروني تم التحقق منه على nitap.ac.in