متابعة
Jose T. de Sousa
Jose T. de Sousa
INESC-ID / Tecnico University of Lisbon
بريد إلكتروني تم التحقق منه على inesc-id.pt
عنوان
عدد مرات الاقتباسات
عدد مرات الاقتباسات
السنة
Moving deep learning to the edge‏
MP Véstias, RP Duarte, JT de Sousa, HC Neto‏
Algorithms 13 (5), 125, 2020‏
762020
A Full Featured Configurable Accelerator for Object Detection with YOLO‏
D Pestana, PR Miranda, JD Lopes, RP Duarte, M Véstias, H C. Neto, ...‏
IEEE Access, 2021‏
742021
Defect level evaluation in an IC design environment‏
JT De Sousa, FM Gonçalves, JP Teixeira, C Marzocca, F Corsi, ...‏
IEEE transactions on computer-aided design of integrated circuits and …, 1996‏
711996
Network core access architecture‏
JT De Sousa, NCC Lourenco, NGDR Ribeiro, VMG Martins, RJS Martins‏
US Patent 8,019,832, 2011‏
602011
A SAT Solver using Reconfigurable Hardware and Virtual Logic‏
M Abramovici, J.T. de Sousa‏
SAT 2000, Highlights of Satisfiability Research in the Year 2000,, 377-402, 2001‏
532001
IC Defects-Based Testability Analysis‏
JJT Sousa, FM Gonçalves, ...‏
International Test Conference (ITC), 500-509, 1991‏
501991
A massively-parallel easily-scalable satisfiability solver using reconfigurable hardware‏
M Abramovici, JT de Sousa, D Saab‏
Proceedings of the 36th annual ACM/IEEE Design Automation Conference, 684-690, 1999‏
491999
Virtual logic system for solving satisfiability problems using reconfigurable hardware‏
M Abramovici, JT De Sousa‏
US Patent 6,442,732, 2002‏
442002
A configurable hardware/software approach to SAT solving‏
JT de Sousa, JM Da Silva, M Abramovici‏
The 9th Annual IEEE Symposium on Field-Programmable Custom Computing …, 2001‏
442001
A 1.7-mW -92-dBm Sensitivity Low-IF Receiver in 0.13-μm CMOS for Bluetooth LE Applications.‏
M Pereira, J T. de Sousa, J Freire, J Vaz‏
IEEE Transactions on Microwave Theory and Techniques, 1-15, 2018‏
38*2018
Parallel Dot-Products for Deep Learning on FPGA‏
M Véstias, R Duarte, JT de Sousa, H Neto‏
27th Int. Conference on Field Programmable Logic and Applications, 2017‏
382017
Parallel backtracing for satisfiability on reconfigurable hardware‏
M Abramovici, JT De Sousa, DG Saab‏
US Patent 6,292,916, 2001‏
342001
Reducing the complexity of defect level modeling using the clustering effect‏
JT de Sousa, VD Agrawal‏
Proceedings Design, Automation and Test in Europe Conference and Exhibition …, 2000‏
342000
Physical DFT for High Coverage of Realistic Faults‏
M Saraiva, P Casimiro, M Santos, JT Sousa, FM Gonçalves, I Teixeira, ...‏
Int. Test Conference (ITC), 642-651, 1992‏
291992
A fast and scalable architecture to run convolutional neural networks in low density FPGAs‏
MP Véstias, RP Duarte, JT de Sousa, HC Neto‏
Microprocessors and Microsystems 77, 103136, 2020‏
282020
Fault Modeling and Defect Level Projections in Digital ICs‏
JT Sousa, FM Gonçalves, JP Teixeira, TW Williams‏
European Design and Test Conference (ED&TC), 436-442, 1994‏
241994
Fast convolutional neural networks in low density FPGAs using zero-skipping and weight pruning‏
MP Véstias, RP Duarte, JT de Sousa, HC Neto‏
Electronics 8 (11), 1321, 2019‏
222019
Lite-CNN: A High-Performance Architecture to Execute CNNs in Low Density FPGAs‏
HN Mário P. Véstias, Rui Policarpo Duarte, José T. de Sousa‏
28th International Conference on Field Programmable Logic and Applications (FPL), 2018‏
222018
Versat, a Minimal Coarse-Grain Reconfigurable Array‏
JD Lopes, JT de Sousa‏
12th International Meeting on High-Performance Computing for Computational …, 2016‏
212016
Fault simulation using partially reconfigurable hardware‏
A Parreira, JP Teixeira, A Pantelimon, MB Santos, JT de Sousa‏
Field Programmable Logic and Application: 13th International Conference, FPL …, 2003‏
212003
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مقالات 1–20