| Low-cost implementation of bilinear and bicubic image interpolation for real-time image super-resolution D Khaledyan, A Amirany, K Jafari, MH Moaiyeri, AZ Khuzani, N Mashhadi 2020 IEEE Global Humanitarian Technology Conference (GHTC), 1-5, 2020 | 64 | 2020 |
| Fully nonvolatile and low power full adder based on spin transfer torque magnetic tunnel junction with spin-hall effect assistance A Amirany, R Rajaei IEEE Transactions on Magnetics 54 (12), 1-7, 2018 | 59 | 2018 |
| Nonvolatile associative memory design based on spintronic synapses and CNTFET neurons A Amirany, MH Moaiyeri, K Jafari IEEE Transactions on Emerging Topics in Computing 10 (1), 428-437, 2020 | 50 | 2020 |
| True random number generator for reliable hardware security modules based on a neuromorphic variation-tolerant spintronic structure A Amirany, K Jafari, MH Moaiyeri IEEE Transactions on Nanotechnology 19, 784-791, 2020 | 41 | 2020 |
| Nonvolatile, Spin-Based, and Low-Power Inexact Full Adder Circuits for Computing-in-Memory Image Processing A Amirany, R Rajaei SPIN, 2019 | 40 | 2019 |
| Process-in-memory using a magnetic-tunnel-junction synapse and a neuron based on a carbon nanotube field-effect transistor A Amirany, MH Moaiyeri, K Jafari IEEE Magnetics Letters 10, 1-5, 2019 | 38 | 2019 |
| Nonvolatile spin-based radiation hardened retention latch and flip-flop A Amirany, F Marvi, K Jafari, R Rajaei IEEE Transactions on Nanotechnology 18, 1089-1096, 2019 | 37 | 2019 |
| High-Performance Spintronic Nonvolatile Ternary Flip-Flop and Universal Shift Register A Amirany, K Jafari, MH Moaiyeri IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2021 | 35 | 2021 |
| Nonvolatile Low-Cost Approximate Spintronic Full-Adders for Computing in Memory Architectures R Rajaei, A Amirany IEEE Transactions on Magnetics, 2020 | 33 | 2020 |
| A low-cost highly reliable spintronic true random number generator circuit for secure cryptography I Alibeigi, A Amirany, R Rajaei, M Tabandeh, SB Shouraki Spin 10 (01), 2050003, 2020 | 31 | 2020 |
| High-Performance Radiation-Hardened Spintronic Retention Latch and Flip-Flop for Highly Reliable Processors A Amirany, K Jafari, MH Moaiyeri IEEE Transactions on Device and Materials Reliability, 2021 | 30 | 2021 |
| Spin-based Fully Nonvolatile Full-Adder Circuit for Computing in Memory A Amirany, R Rajaei SPIN 3, 5, 2019 | 24 | 2019 |
| Reliable, high-performance, and nonvolatile hybrid SRAM/MRAM-based structures for reconfigurable nanoscale logic devices R Rajaei, A Amirany Journal of Nanoelectronics and Optoelectronics 13 (9), 1271-1283, 2018 | 24 | 2018 |
| Low Power, and Highly Reliable Single Event Upset Immune Latch for Nanoscale CMOS Technologies A Amirany, R Rajaei 26th Iranian Conference on Electrical Engineering (ICEE2018), 103-107, 2018 | 24 | 2018 |
| High-Performance and Robust Spintronic/CNTFET-based Binarized Neural Network Hardware Accelerator M Tanavardi Nasab, A Amirany, MH Moaiyeri, K Jafari IEEE Transactions on Emerging Topics in Computing, 2022 | 23 | 2022 |
| DDR-MRAM: Double Data Rate Magnetic RAM for Efficient Artificial Intelligence and Cache Applications A Amirany, K Jafari, MH Moaiyeri IEEE Transactions on Magnetics 58 (6), 1-9, 2022 | 23 | 2022 |
| TS-NSFPGA: A Task Schedulable Non-volatile Spintronic FPGA A Amirany, K Jafari, MH Moaiyeri IEEE Magnetics Letters, 2021 | 23* | 2021 |
| Stochastic spintronic neuron with application to image binarization A Amirany, M Meghdadi, MH Moaiyeri, K Jafari 2021 26th International Computer Conference, Computer Society of Iran (CSICC …, 2021 | 23 | 2021 |
| High-performance and soft error immune spintronic retention latch for highly reliable processors A Amirany, K Jafari, MH Moaiyeri 2020 28th Iranian Conference on Electrical Engineering (ICEE), 1-5, 2020 | 23 | 2020 |
| An SEU-Hardened Ternary SRAM Design Based on Efficient Ternary C-Elements Using CNTFET Technology V Bakhtiary, A Amirany, MH Moaiyeri, K Jafari Microelectronics Reliability 140, 114881, 2023 | 22 | 2023 |