| Encrypted memory AF Glew, DA Gerrity, CT Tegreene US Patent 8,930,714, 2015 | 332 | 2015 |
| Security perimeter AF Glew, DA Gerrity, CT Tegreene US Patent 9,575,903, 2017 | 319 | 2017 |
| Method for pipeline processing of instructions by controlling access to a reorder buffer using a register file outside the reorder buffer GJ Hinton, DB Papworth, AF Glew, MA Fetterman, RP Colwell US Patent 5,721,855, 1998 | 224 | 1998 |
| System and method for protection against untrusted system management code by redirecting a system management interrupt and creating a virtual machine container J Sutton, D Grawrock, R Uhlig, D Poisner, A Glew, C Hall, L Smith, ... US Patent App. 10/165,597, 2003 | 166 | 2003 |
| Fine-grained security in federated data sets AF Glew, DA Gerrity, CT Tegreene US Patent 8,943,313, 2015 | 155 | 2015 |
| MLP yes! ILP no A Glew ASPLOS Wild and Crazy Idea Session 98, 1998 | 153 | 1998 |
| Lens system Y Shinohara US Patent 10,185,123, 2019 | 142* | 2019 |
| Authenticated code module AF Glew, JA Sutton, LO Smith, DW Grawrock, G Neiger, MA Kozuch US Patent 7,308,576, 2007 | 129 | 2007 |
| Method and apparatus for executing two types of instructions that specify registers of a shared logical register file in a stack and a non-stack referenced manner D Lin, RR Vakkalagadda, AF Glew, LM Mennemeier, AD Peleg, D Bistry, ... US Patent 5,852,726, 1998 | 125 | 1998 |
| Method and apparatus for implementing a single clock cycle line replacement in a data cache unit H Akkary, MS Joshi, R Murray, BE Lince, PD Madland, AF Glew, ... US Patent 5,526,510, 1996 | 118 | 1996 |
| Processor supporting execution of an authenticated code instruction A Glew, J Sutton, L Smith, D Grawrock, G Neiger, M Kozuch US Patent App. 10/039,961, 2003 | 115 | 2003 |
| Methods and systems to control virtual machines SM Bennett, G Neiger, EC Cota-Robles, S Jeyasingh, A Kagi, MA Kozuch, ... US Patent 7,318,141, 2008 | 114 | 2008 |
| Method and apparatus for handling speculative memory access operations AF Glew, H Akkary US Patent 5,956,753, 1999 | 112 | 1999 |
| Fault-tolerant boot strap mechanism for a multiprocessor system M Karnik, J Batz, K Tiruvallur, A Glew, F Binns, S Thakkar, N Sarangdhar US Patent 5,724,527, 1998 | 103 | 1998 |
| Out-of-order processor with a memory subsystem which handles speculatively dispatched load operations JM Abramson, DB Papworth, HH Akkary, AF Glew, GJ Hinton, ... US Patent 5,751,983, 1998 | 102 | 1998 |
| Method and apparatus for processing memory-type information within a microprocessor AF Glew, GJ Hinton US Patent 5,751,996, 1998 | 101 | 1998 |
| System and method for controlling switching between VMM and VM using enabling value of VMM timer indicator and VMM timer value having a specified time G Neiger, SM Bennett, E Cota-Robles, S Schoenberg, CD Hall, ... US Patent 7,840,962, 2010 | 100 | 2010 |
| Method and apparatus for dynamic allocation of multiple buffers in a processor DB Papworth, AF Glew, GJ Hinton, RP Colwell, MA Fetterman, SR Gupta, ... US Patent 5,778,245, 1998 | 93 | 1998 |
| Methods and apparatus for caching data in a non-blocking manner using a plurality of fill buffers H Akkary, JM Abramson, AF Glew, GJ Hinton, KG Konigsfeld, PD Madland, ... US Patent 5,671,444, 1997 | 90 | 1997 |
| Branch target buffer for dynamically predicting branch instruction outcomes using a predicted branch history BD Hoyt, GJ Hinton, AF Glew, S Natarajan US Patent 5,584,001, 1996 | 87 | 1996 |
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