On topology reconfiguration for defect-tolerant NoC-based homogeneous manycore systems L Zhang, Y Han, Q Xu, X wei Li, H Li IEEE Transactions on Very Large Scale Integration (VLSI) Systems 17 (9 …, 2009 | 93 | 2009 |
Defect tolerance in homogeneous manycore processors using core-level redundancy with unified topology L Zhang, Y Han, Q Xu, X Li Proceedings of the conference on Design, automation and test in Europe, 891-896, 2008 | 82 | 2008 |
Vertical interconnects squeezing in symmetric 3D mesh network-on-chip C Liu, L Zhang, Y Han, X Li 16th Asia and South Pacific Design Automation Conference (ASP-DAC 2011), 357-362, 2011 | 81 | 2011 |
Linear Symmetric Quantization of Neural Networks for Low-precision Integer Hardware X Zhao, Y Wang, X Cai, C Liu, L Zhang International Conference on Learning Representations, 2019 | 80 | 2019 |
Thermal-constrained task allocation for interconnect energy reduction in 3-D homogeneous MPSoCs Y Cheng, L Zhang, Y Han, X Li IEEE Transactions on Very Large Scale Integration (VLSI) Systems 21 (2), 239-249, 2012 | 74 | 2012 |
Wear rate leveling: lifetime enhancement of PRAM with endurance variation J Dong, L Zhang, Y Han, Y Wang, X Li Proceedings of the 48th Design Automation Conference, 972-977, 2011 | 70 | 2011 |
Reliability evaluation and analysis of fpga-based neural network acceleration system D Xu, Z Zhu, C Liu, Y Wang, S Zhao, L Zhang, H Liang, H Li, KT Cheng IEEE Transactions on Very Large Scale Integration (VLSI) Systems 29 (3), 472-484, 2021 | 41 | 2021 |
ProPRAM: exploiting the transparent logic resources in non-volatile memory for near data computing Y Wang, Y Han, L Zhang, H Li, X Li Proceedings of the 52nd Annual Design Automation Conference, 1-6, 2015 | 38 | 2015 |
A resilient on-chip router design through data path salvaging C Liu, L Zhang, Y Han, X Li 16th Asia and South Pacific Design Automation Conference (ASP-DAC 2011), 437-442, 2011 | 38 | 2011 |
RaQu: An automatic high-utilization CNN quantization and mapping framework for general-purpose RRAM Accelerator S Qu, B Li, Y Wang, D Xu, X Zhao, L Zhang 2020 57th ACM/IEEE Design Automation Conference (DAC), 1-6, 2020 | 37 | 2020 |
Fault tolerance mechanism in chip many-core processors L Zhang, Y Han, H Li, X Li Tsinghua Science and Technology 12 (S1), 169-174, 2007 | 37 | 2007 |
Economizing TSV resources in 3-D network-on-chip design Y Wang, YH Han, L Zhang, BZ Fu, C Liu, HW Li, X Li IEEE Transactions on Very Large Scale Integration (VLSI) Systems 23 (3), 493-506, 2014 | 36 | 2014 |
BitPruner: network pruning for bit-serial accelerators X Zhao, Y Wang, C Liu, C Shi, K Tu, L Zhang 2020 57th ACM/IEEE Design Automation Conference (DAC), 1-6, 2020 | 31 | 2020 |
A hybrid computing architecture for fault-tolerant deep learning accelerators D Xu, C Chu, Q Wang, C Liu, Y Wang, L Zhang, H Liang, KT Cheng 2020 IEEE 38th International Conference on Computer Design (ICCD), 478-485, 2020 | 28 | 2020 |
You only search once: a fast automation framework for single-stage DNN/Accelerator co-design W Chen, Y Wang, S Yang, C Liu, L Zhang 2020 Design, Automation & Test in Europe Conference & Exhibition (DATE …, 2020 | 26 | 2020 |
Resilient Neural Network Training for Accelerators with Computing Errors D Xu, K Xing, C Liu, Y Wang, Y Dai, L Cheng, H Li, L Zhang 2019 IEEE 30th International Conference on Application-specific Systems …, 2019 | 24 | 2019 |
Optimus: An Operator Fusion Framework for Deep Neural Networks X Cai, Y Wang, L Zhang ACM Transactions on Embedded Computing Systems 22 (1), 1-26, 2022 | 22 | 2022 |
用于片上网络的容错通信算法 张磊, 李华伟, 李晓维 计算机辅助设计与图形学学报 19 (4), 508-514, 2007 | 20 | 2007 |
Network-on-Interposer Design for Agile Neural-Network Processor Chip Customization M Wang, Y Wang, C Liu, L Zhang 2021 58th ACM/IEEE Design Automation Conference (DAC), 49-54, 2021 | 19 | 2021 |
DeepBurning-SEG: Generating DNN Accelerators of Segment-Grained Pipeline Architecture X Cai, Y Wang, X Ma, Y Han, L Zhang 2022 55th IEEE/ACM International Symposium on Microarchitecture (MICRO …, 2022 | 18 | 2022 |