| Understanding Energy Efficiency Benefits of Carbon Nanotube Field-Effect Transistors for Digital VLSI G Hills, MG Bardon, G Doornbos, D Yakimets, P Schuddinck, R Baert, ... IEEE Transactions on Nanotechnology 17 (6), 1259-1269, 2018 | 145 | 2018 |
| Buried Power Rails and Back-side Power Grids: Arm® CPU Power Delivery Network Design Beyond 5nm D Prasad, SST Nibhanupudi, S Das, O Zografos, B Chehab, S Sarkar, ... 2019 IEEE International Electron Devices Meeting (IEDM), 19.1. 1-19.1. 4, 2019 | 82 | 2019 |
| Extreme scaling enabled by 5 tracks cells: holistic design-device co-optimization for FinFETs and lateral nanowires M Garcia Bardon, Y Sherazi, P Schuddinck, D Jang, D Yakimets, ... IEEE International Electron Devices Meeting-IEDM, 687-690, 2016 | 82* | 2016 |
| Towards 10000TOPS/W DNN Inference with Analog in-Memory Computing–A Circuit Blueprint, Device Options and Requirements S Cosemans, B Verhoef, J Doevenspeck, IA Papistas, F Catthoor, ... 2019 IEEE International Electron Devices Meeting (IEDM), 22.2. 1-22.2. 4, 2019 | 78 | 2019 |
| SOT-MRAM based analog in-memory computing for DNN inference J Doevenspeck, K Garello, B Verhoef, R Degraeve, S Van Beek, D Crotti, ... 2020 IEEE Symposium on VLSI Technology, 1-2, 2020 | 75 | 2020 |
| DIANA: An End-to-End Energy-Efficient Digital and ANAlog Hybrid Neural Network SoC K Ueyoshi, IA Papistas, P Houshmand, GM Sarda, V Jain, M Shi, Q Zheng, ... 2022 IEEE International Solid-State Circuits Conference (ISSCC) 65, 1-3, 2022 | 71 | 2022 |
| The impact of sequential-3D integration on semiconductor scaling roadmap A Mallik, A Vandooren, L Witters, A Walke, J Franco, Y Sherazi, P Weckx, ... 2017 IEEE International Electron Devices Meeting (IEDM), 32.1. 1-31.1. 4, 2017 | 60 | 2017 |
| DIANA: An End-to-End Hybrid DIgital and ANAlog Neural Network SoC for the Edge P Houshmand, GM Sarda, V Jain, K Ueyoshi, IA Papistas, M Shi, Q Zheng, ... IEEE Journal of Solid-State Circuits 58 (1), 203-215, 2022 | 51 | 2022 |
| A 22 nm, 1540 TOP/s/W, 12.1 TOP/s/mm2 in-Memory Analog Matrix-Vector-Multiplier for DNN Acceleration IA Papistas, S Cosemans, B Rooseleer, J Doevenspeck, MH Na, A Mallik, ... 2021 IEEE Custom Integrated Circuits Conference (CICC), 1-2, 2021 | 49 | 2021 |
| Technology/system codesign and benchmarking for lateral and vertical GAA nanowire FETs at 5-nm technology node C Pan, P Raghavan, D Yakimets, P Debacker, F Catthoor, N Collaert, ... IEEE Transactions on Electron Devices 62 (10), 3125-3132, 2015 | 49 | 2015 |
| Integrated circuit power distribution network P Debacker, P Raghavan, VC Gerousis US Patent 10,510,774, 2019 | 45 | 2019 |
| Dynamic time-slot allocation for QoS enabled networks on chip T Marescaux, B Bricke, P Debacker, V Nollet, H Corporaal 3rd Workshop on Embedded Systems for Real-Time Multimedia, 2005., 47-52, 2005 | 44 | 2005 |
| Sub-word parallel precision-scalable MAC engines for efficient embedded DNN inference L Mei, M Dandekar, D Rodopoulos, J Constantin, P Debacker, ... 2019 IEEE International Conference on Artificial Intelligence Circuits and …, 2019 | 43 | 2019 |
| Neural network accelerator comparison K Guo, W Li, K Zhong, Z Zhu, S Zeng, S Han, Y Xie, P Debacker, ... NICS Lab of Tsinghua University. http://nicsefc. ee. tsinghua. edu. cn …, 2021 | 42 | 2021 |
| Design-technology co-optimization for OxRRAM-based synaptic processing unit A Mallik, D Garbin, A Fantini, D Rodopoulos, R Degraeve, J Stuijt, AK Das, ... 2017 Symposium on VLSI Technology, T178-T179, 2017 | 42 | 2017 |
| Standard cell design in N7: EUV vs. immersion B Chava, D Rio, Y Sherazi, D Trivkovic, W Gillijns, P Debacker, ... Design-Process-Technology Co-optimization for Manufacturability IX 9427, 110-118, 2015 | 39 | 2015 |
| SEMICONDUCTOR CELL CONFIGURED TO PERFORM LOGIC OPERATIONS D Garbin, D Rodopoulos, P Debacker, P Raghavan US Patent App. 15/820,239, 2018 | 35 | 2018 |
| DTCO exploration for efficient standard cell power rails B Chava, J Ryckaert, L Mattii, SMY Sherazi, P Debacker, A Spessot, ... Design-Process-Technology Co-optimization for Manufacturability XII 10588, 89-94, 2018 | 34 | 2018 |
| Standard-cell design architecture options below 5nm node: The ultimate scaling of FinFET and Nanosheet SMY Sherazi, M Cupak, P Weckx, O Zografos, D Jang, P Debacker, ... Design-Process-Technology Co-optimization for Manufacturability XIII 10962 …, 2019 | 33 | 2019 |
| Low track height standard cell design in iN7 using scaling boosters SMY Sherazi, C Jha, D Rodopoulos, P Debacker, B Chava, L Matti, ... Design-Process-Technology Co-optimization for Manufacturability XI 10148 …, 2017 | 33 | 2017 |
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