| CaDiCaL 2.0 A Biere, T Faller, K Fazekas, M Fleury, N Froleyks, F Pollitt International Conference on Computer Aided Verification, 133-152, 2024 | 16 | 2024 |
| Effective SAT-based solutions for generating functional sequences maximizing the sustained switching activity in a pipelined processor NI Deligiannis, R Cantoro, T Faller, T Paxian, B Becker, MS Reorda 2021 IEEE 30th Asian Test Symposium (ATS), 73-78, 2021 | 13 | 2021 |
| Constraint-based automatic SBST generation for RISC-V processor families T Faller, NI Deligiannis, M Schwörer, MS Reorda, B Becker 2023 IEEE European Test Symposium (ETS), 1-6, 2023 | 12 | 2023 |
| Towards SAT-based SBST generation for RISC-V cores T Faller, P Scholl, T Paxian, B Becker 2021 IEEE 22nd Latin American Test Symposium (LATS), 1-2, 2021 | 9 | 2021 |
| Using formal methods to support the development of STLs for GPUs NI Deligiannis, T Faller, JER Condia, R Cantoro, B Becker, MS Reorda 2022 IEEE 31st Asian Test Symposium (ATS), 84-89, 2022 | 8 | 2022 |
| A survey of recent developments in testability, safety and security of risc-v processors J Anders, P Andreu, B Becker, S Becker, R Cantoro, NI Deligiannis, ... 2023 IEEE European Test Symposium (ETS), 1-10, 2023 | 7 | 2023 |
| Automating the generation of programs maximizing the repeatable constant switching activity in microprocessor units via MaxSAT NI Deligiannis, T Faller, R Cantoro, T Paxian, B Becker, MS Reorda IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2023 | 7 | 2023 |
| CaDiCaL, Gimsatul, IsaSAT and Kissat Entering the SAT Competition 2024 A Biere, T Faller, K Fazekas, M Fleury, N Froleyks, F Pollitt SAT COMPETITION 2024, 8, 2024 | 2 | 2024 |
| Automatic Identification of Functionally Untestable Cell-Aware Faults in Microprocessors NI Deligiannis, T Faller, I Guglielminetti, R Cantoro, B Becker, MS Reorda 2023 IEEE 32nd Asian Test Symposium (ATS), 1-6, 2023 | 2 | 2023 |
| Automating the Generation of Functional Stress Inducing Stimuli for Burn-In Testing NI Deligiannis, T Faller, Z Chenghan, R Cantoro, B Becker, MS Reorda 2023 IEEE European Test Symposium (ETS), 1-5, 2023 | 2 | 2023 |
| Enhancing the effectiveness of STLs for GPUs via bounded model checking N Deligiannis, T Faller, JE Rodriguez Condia, R Cantoro, B Becker, ... ACM Transactions on Design Automation of Electronic Systems 30 (2), 1-24, 2025 | 1 | 2025 |
| Special Session: Software-Based Self-Test Generation for RISC-V–Stuck-At Generation, Functional Cell-Aware Untestability, and FPGA Demonstration– T Faller, NI Deligiannis, R Cantoro, MS Reorda, B Becker 2024 IEEE International Symposium on Defect and Fault Tolerance in VLSI and …, 2024 | | 2024 |
| Scale4Edge-Scaling RISC-V for Edge Applications W Ecker, M Krstic, M Ulbricht, A Mauderer, E Jentzsch, A Koch, ... | | 2023 |
| Hardware Equivalence Checking Problems Submitted to the SAT Competition 2024 A Biere, T Faller, K Fazekas, M Fleury, N Froleyks, F Pollitt SAT COMPETITION 2024, 33, 0 | | |
