| A new dimension of parallelism in ultra high throughput LDPC decoding P Schläfer, N Wehn, M Alles, T Lehnigk-Emden Signal Processing Systems (SiPS), 2013 IEEE Workshop on, 153-158, 2013 | 85 | 2013 |
| Saturated Min-Sum Decoding: An “Afterburner” for LDPC Decoder Hardware S Scholl, P Schläfer, N Wehn IEEE Design, Automation and Test in Europe (DATE), 2016 | 25 | 2016 |
| Syndrome based check node processing of high order NB-LDPC decoders P Schläfer, N Wehn, M Alles, T Lehnigk-Emden, E Boutillon Telecommunications (ICT), 2015 22nd International Conference on, 156-162, 2015 | 25 | 2015 |
| Design space of flexible multigigabit LDPC decoders P Schläfer, C Weis, N Wehn, M Alles VLSI Design 2012 (1), 942893, 2012 | 25 | 2012 |
| A new Architecture for High Throughput, Low Latency NB-LDPC Check Node Processing P Schläfer, V Rybalkin, N Wehn, M Alles, T Lehnigk-Emden, E Boutillon International Symposium on Personal, Indoor and Mobile Radio Communications …, 2015 | 13* | 2015 |
| Challenges and limitations for very high throughput decoder architectures for soft-decoding N Wehn, S Scholl, P Schläfer, T Lehnigk-Emden, M Alles Advanced Hardware Design for Error Correcting Codes, 7-31, 2015 | 13 | 2015 |
| A new Architecture for High Speed, Low Latency NB-LDPC Check Node Processing for GF(256) V Rybalkin, P Schläfer, N Wehn IEEE Vehicular Technology Conference (VTC), 2016 | 11 | 2016 |
| Error Resilience and Energy Efficiency: An LDPC Decoder Design Study P Schläfer, C Huang, C Shoeny, C Weis, Y Li, N Wehn, L Dolecek IEEE Design, Automation and Test in Europe (DATE), 2016 | 8 | 2016 |
| A New LDPC Decoder Hardware Implementation with Improved Error Rates P Schläfer, S Scholl, E Leonardi, N Wehn IEEE Jordan Conference on Applied Electrical Engineering and Computing …, 2015 | 8 | 2015 |
| Loopy—an open-source tcp/ip rapid prototyping and validation framework C De Schryver, P Schläfer, N Wehn, T Fischer, A Poetzsch-Heffter Reconfigurable Computing and FPGAs (ReConFig), 2013 International Conference …, 2013 | 3 | 2013 |
| ASIC implementation of a modified QR decomposition for tree search based MIMO detection C Gimmler-Dumont, P Schläfer, N Wehn Circuits and Systems (LASCAS), 2013 IEEE Fourth Latin American Symposium on, 1-4, 2013 | 3 | 2013 |
| FPGA-based rapid prototyping platform for MIMO-BICM design space exploration C Gimmler-Dumont, P Schläfer, N Wehn Reconfigurable Computing and FPGAs (ReConFig), 2012 International Conference …, 2012 | 2 | 2012 |
| Method for controlling a check node of a NB-LDPC decoder and corresponding check node E Boutillon, P Schläfer, T Lehnigk-Emden US Patent 10,554,226, 2020 | | 2020 |
| Implementation Aspects of Binary and Non-binary Low-density Parity-check Decoders: Implementierungsaspekte Binärer und Nicht-binärer Kanaldecodierer P Schläfer Technische Universität Kaiserslautern, 2017 | | 2017 |
Norbert WehnUniversity of Kaiserslauternبريد إلكتروني تم التحقق منه على eit.uni-kl.de