A 3.6 GHz low-noise fractional-N digital PLL using SAR-ADC-based TDC Z Xu, M Miyahara, K Okada, A Matsuzawa
IEEE Journal of Solid-State Circuits 51 (10), 2345-2356, 2016
48 2016 A 0.84 ps-LSB 2.47 mW time-to-digital converter using charge pump and SAR-ADC Z Xu, S Lee, M Miyahara, A Matsuzawa
Proceedings of 2013 IEEE Custom Integrated Circuits Conference, 1-4, 2013
45 2013 Picosecond Resolution Time-to-Digital Converter Using Z Xu, M Miyahara, A Matsuzawa
IEEE Transactions on Nuclear Science 61 (2), 852-859, 2014
24 2014 An HDL-described Fully-synthesizable Sub-GHz IoT Transceiver with Ring Oscillator based Frequency Synthesizer and Digital Background EVM Calibration B Liu, Y Zhang, J Qiu, W Deng, Z Xu, H Zhang, J Pang, Y Wang, R Wu, ...
Proceedings of 2019 IEEE Custom Integrated Circuits Conference (CICC), 1-4, 2019
18 2019 An all-standard-cell-based synthesizable SAR ADC with nonlinearity-compensated RDAC Z Xu, N Ojima, S Li, T Iizuka
IEEE Transactions on Very Large Scale Integration (VLSI) Systems 29 (12 …, 2021
16 2021 A 3.2-to-3.8 GHz harmonic-mixer-based dual-feedback fractional-N PLL achieving-65 dBc in-band fractional spur M Osada, Z Xu, T Iizuka
IEEE Solid-State Circuits Letters 3, 534-537, 2020
13 2020 A 0.0053-mm2 6-bit Fully-Standard-Cell-Based Synthesizable SAR ADC in 65 nm CMOS N Ojima, Z Xu, T Iizuka
2019 17th IEEE International New Circuits and Systems Conference (NEWCAS), 1-4, 2019
13 2019 A 1 ps-resolution integrator-based time-to-digital converter using a sar-adc in 90nm cmos Z Xu, M Miyahara, A Matsuzawa
Proceedings of the IEEE 2013 International New Circuits and Systems …, 2013
10 2013 Ultralow-power class-C complementary colpitts crystal oscillator Z Xu, N Kimura, K Okada, M Miyahara
IEEE Solid-State Circuits Letters 3, 274-277, 2020
9 2020 A 2 GHz 3.1 mW type-I digital ring-based PLL Z Xu, A Firdauzi, M Miyahara, K Okada, A Matsuzawa
Proceedings of 2016 IEEE European Solid-State Circuits Conference (ESSCIRC …, 2016
9 2016 A 0.5-to-1 V 9-bit 15-to-90 MS/s digitally interpolated pipelined-SAR ADC using dynamic amplifier J Lin, Z Xu, M Miyahara, A Matsuzawa
Proceedings of 2014 IEEE Asian Solid-State Circuits Conference (A-SSCC), 85-88, 2014
9 2014 Self-dithered digital delta-sigma modulators for fractional-N PLL Z Xu, JG Lee, S Masui
IEICE Transactions on Electronics 94 (6), 1065-1068, 2011
9 2011 A 3.2-to-3.8 GHz Calibration-Free Harmonic-Mixer-Based Dual-Feedback Fractional-N PLL Achieving–66dBc Worst-Case In-Band Fractional Spur M Osada, Z Xu, T Iizuka
2020 IEEE Symposium on VLSI Circuits, 1-2, 2020
7 2020 A 74.9 dB SNDR 1 MHz bandwidth 0.9 mW delta-sigma time-to-digital converter using charge pump and SAR ADC A Firdauzi, Z Xu, M Miyahara, A Matsuzawa
Proceedings of 2016 IEEE International Symposium on Circuits and Systems …, 2016
7 2016 A 10-GHz inductorless cascaded PLL with zero-ISF subsampling phase detector achieving− 63-dBc reference spur, 175-fs RMS jitter and− 240-dB FOMjitter Z Yang, Z Xu, M Osada, T Iizuka
2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and …, 2022
6 2022 Robustness Evaluation of Restricted Boltzmann Machine against Memory and Logic Error Y Fukuda, Z Xu, T Kawahara
IEICE Transactions on Electronics 100 (12), 1118-1121, 2017
6 2017 Sub-picosecond resolution and high-precision TDC for ADPLLs using charge pump and SAR-ADC Z Xu, S Lee, M Miyahara, A Matsuzawa
IEICE Transactions on Fundamentals of Electronics, Communications and …, 2015
6 2015 Analysis and simulation of MOSFET-based gate-voltage-independent capacitor S Li, N Ojima, Z Xu, T Iizuka
Japanese Journal of Applied Physics 61 (6), 064501, 2022
5 2022 A 3.3-GHz 4.6-mW fractional-N type-II hybrid switched-capacitor sampling PLL using CDAC-embedded digital integral path with− 80-dBc reference spur Z Xu, M Osada, T Iizuka
2021 Symposium on VLSI Circuits, 1-2, 2021
5 2021 A fractional-N ring PLL using harmonic-mixer-based dual-feedback and split-feedback frequency division with phase-domain filtering M Osada, Z Xu, Z Yang, T Iizuka
IEEE Journal of Solid-State Circuits 59 (7), 2171-2184, 2024
4 2024 