| Revisiting rowhammer: An experimental analysis of modern dram devices and mitigation techniques JS Kim, M Patel, AG Yağlıkçı, H Hassan, R Azizi, L Orosa, O Mutlu 2020 ACM/IEEE 47th Annual International Symposium on Computer Architecture …, 2020 | 213 | 2020 |
| Robust machine learning systems: Challenges, current trends, perspectives, and the road ahead M Shafique, M Naseer, T Theocharides, C Kyrkou, O Mutlu, L Orosa, ... IEEE Design & Test 37 (2), 30-57, 2020 | 153 | 2020 |
| EDEN: Enabling energy-efficient, high-performance deep neural network inference using approximate DRAM S Koppula, L Orosa, AG Yağlıkçı, R Azizi, T Shahroodi, K Kanellopoulos, ... Proceedings of the 52nd Annual IEEE/ACM International Symposium on …, 2019 | 153 | 2019 |
| Blockhammer: Preventing rowhammer at low cost by blacklisting rapidly-accessed dram rows AG Yağlikçi, M Patel, JS Kim, R Azizi, A Olgun, L Orosa, H Hassan, J Park, ... 2021 IEEE International Symposium on High-Performance Computer Architecture …, 2021 | 141 | 2021 |
| D-RaNGe: Using commodity DRAM devices to generate true random numbers with low latency and high throughput JS Kim, M Patel, H Hassan, L Orosa, O Mutlu 2019 IEEE International Symposium on High Performance Computer Architecture …, 2019 | 127 | 2019 |
| DAMOV: A new methodology and benchmark suite for evaluating data movement bottlenecks GF Oliveira, J Gómez-Luna, L Orosa, S Ghose, N Vijaykumar, I Fernandez, ... IEEE Access 9, 134457-134502, 2021 | 108 | 2021 |
| FLIN: Enabling fairness and enhancing performance in modern NVMe solid state drives A Tavakkol, M Sadrosadati, S Ghose, J Kim, Y Luo, Y Wang, NM Ghiasi, ... 2018 ACM/IEEE 45th Annual International Symposium on Computer Architecture …, 2018 | 104 | 2018 |
| Syncron: Efficient synchronization support for near-data-processing architectures C Giannoula, N Vijaykumar, N Papadopoulou, V Karakostas, I Fernandez, ... 2021 IEEE International Symposium on High-Performance Computer Architecture …, 2021 | 99 | 2021 |
| A deeper look into rowhammer’s sensitivities: Experimental analysis of real dram chips and implications on future attacks and defenses L Orosa, AG Yaglikci, H Luo, A Olgun, J Park, H Hassan, M Patel, JS Kim, ... MICRO-54: 54th Annual IEEE/ACM International Symposium on Microarchitecture …, 2021 | 97 | 2021 |
| FIGARO: Improving system performance via fine-grained in-DRAM data relocation and caching Y Wang, L Orosa, X Peng, Y Guo, S Ghose, M Patel, JS Kim, JG Luna, ... 2020 53rd Annual IEEE/ACM International Symposium on Microarchitecture …, 2020 | 92 | 2020 |
| CLR-DRAM: A low-cost DRAM architecture enabling dynamic capacity-latency trade-off H Luo, T Shahroodi, H Hassan, M Patel, AG Yağlıkçı, L Orosa, J Park, ... 2020 ACM/IEEE 47th Annual International Symposium on Computer Architecture …, 2020 | 63 | 2020 |
| Reducing DRAM latency via charge-level-aware look-ahead partial restoration Y Wang, A Tavakkol, L Orosa, S Ghose, NM Ghiasi, M Patel, JS Kim, ... 2018 51st Annual IEEE/ACM International Symposium on Microarchitecture …, 2018 | 59 | 2018 |
| Understanding rowhammer under reduced wordline voltage: An experimental study using real dram devices AG Yağlıkçı, H Luo, GF De Oliviera, A Olgun, M Patel, J Park, H Hassan, ... 2022 52nd Annual IEEE/IFIP International Conference on Dependable Systems …, 2022 | 56 | 2022 |
| pLUTo: Enabling massively parallel computation in DRAM via lookup tables JD Ferreira, G Falcao, J Gómez-Luna, M Alser, L Orosa, M Sadrosadati, ... 2022 55th IEEE/ACM International Symposium on Microarchitecture (MICRO), 900-919, 2022 | 49 | 2022 |
| Hira: Hidden row activation for reducing refresh latency of off-the-shelf dram chips AG Yağlikci, A Olgun, M Patel, H Luo, H Hassan, L Orosa, O Ergin, ... 2022 55th IEEE/ACM International Symposium on Microarchitecture (MICRO), 815-834, 2022 | 49 | 2022 |
| Reducing solid-state drive read latency by optimizing read-retry J Park, M Kim, M Chun, L Orosa, J Kim, O Mutlu Proceedings of the 26th ACM International Conference on Architectural …, 2021 | 46 | 2021 |
| pluto: In-dram lookup tables to enable massively parallel general-purpose computation JD Ferreira, G Falcao, J Gómez-Luna, M Alser, L Orosa, M Sadrosadati, ... arXiv preprint arXiv:2104.07699, 2021 | 42 | 2021 |
| Codic: A low-cost substrate for enabling custom in-dram functionalities and optimizations L Orosa, Y Wang, M Sadrosadati, JS Kim, M Patel, I Puddu, H Luo, ... 2021 ACM/IEEE 48th Annual International Symposium on Computer Architecture …, 2021 | 40 | 2021 |
| ITAP: Idle-time-aware power management for GPU execution units M Sadrosadati, SB Ehsani, H Falahati, R Ausavarungnirun, A Tavakkol, ... ACM Transactions on Architecture and Code Optimization (TACO) 16 (1), 1-26, 2019 | 36 | 2019 |
| DRAM bender: An extensible and versatile FPGA-based infrastructure to easily test state-of-the-art DRAM chips A Olgun, H Hassan, AG Yağlıkçı, YC Tuğrul, L Orosa, H Luo, M Patel, ... IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2023 | 34 | 2023 |
Onur MutluETH Zürich and Carnegie Mellon UniversityПотвърден имейл адрес: inf.ethz.ch
