| A 0.2 V, 480 kb subthreshold SRAM with 1 k cells per bitline for ultra-low-voltage computing TH Kim, J Liu, J Keane, CH Kim IEEE Journal of Solid-State Circuits 43 (2), 518-529, 2008 | 272 | 2008 |
| An all-in-one silicon odometer for separately monitoring HCI, BTI, and TDDB J Keane, X Wang, D Persaud, CH Kim IEEE Journal of Solid-State Circuits 45 (4), 817-829, 2010 | 241 | 2010 |
| A high-density subthreshold SRAM with data-independent bitline leakage and virtual ground replica scheme TH Kim, J Liu, J Keane, CH Kim Solid-State Circuits Conference, 2007. ISSCC 2007. Digest of Technical …, 2007 | 211 | 2007 |
| An on-chip NBTI sensor for measuring PMOS threshold voltage degradation J Keane, TH Kim, CH Kim IEEE Transactions on Very Large Scale Integration (VLSI) Systems 18 (6), 947-956, 2010 | 184 | 2010 |
| Utilizing reverse short-channel effect for optimal subthreshold circuit design TH Kim, J Keane, H Eom, CH Kim IEEE Transactions on Very Large Scale Integration (VLSI) Systems 15 (7), 821-829, 2007 | 174 | 2007 |
| Subthreshold logical effort: a systematic framework for optimal subthreshold device sizing J Keane, H Eom, TH Kim, S Sapatnekar, C Kim Proceedings of the 43rd annual Design Automation Conference, 425-428, 2006 | 83 | 2006 |
| 17.2 5.6Mb/mm2 1R1W 8T SRAM arrays operating down to 560mV utilizing small-signal sensing with charge-shared bitline and asymmetric sense amplifier in 14nm FinFET CMOS technology J Keane, J Kulkarni, KH Koo, S Nalam, Z Guo, K Karl, Eric, Zhang IEEE International Solid-State Circuits Conference, 2016 | 63* | 2016 |
| 17.1 A 0.6 V 1.5 GHz 84Mb SRAM design in 14nm FinFET CMOS technology E Karl, Z Guo, JW Conary, JL Miller, S Nalam, D Kim, J Keane, K Zhang IEEE International Solid-State Circuits Conference, 2015 | 59 | 2015 |
| An array-based odometer system for statistically significant circuit aging characterization J Keane, W Zhang, CH Kim IEEE Journal of Solid-State Circuits 46 (10), 2374-2385, 2011 | 49 | 2011 |
| An array-based test circuit for fully automated gate dielectric breakdown characterization J Keane, S Venkatraman, P Butzen, CH Kim Custom Integrated Circuits Conference, 2008. CICC 2008. IEEE, 121-124, 2008 | 47 | 2008 |
| Circuit techniques for ultra-low power subthreshold SRAMs TH Kim, J Liu, J Keane, CH Kim 2008 IEEE International Symposium on Circuits and Systems, 2574-2577, 2008 | 39 | 2008 |
| On-chip reliability monitors for measuring circuit degradation J Keane, T Kim, X Wang, CH Kim Microelectronics Reliability 50 (8), 1039-1053, 2010 | 36 | 2010 |
| An odometer for CPUs J Keane, CH Kim Spectrum, IEEE 48 (5), 28-33, 2011 | 34 | 2011 |
| Stack sizing for optimal current drivability in subthreshold circuits J Keane, H Eom, TH Kim, S Sapatnekar, C Kim IEEE Transactions on Very Large Scale Integration Systems 16 (5), 598, 2008 | 30 | 2008 |
| An on-chip monitor for statistically significant circuit aging characterization J Keane, W Zhang, CH Kim Electron Devices Meeting (IEDM), 2010 IEEE International, 4.2. 1-4.2. 4, 2010 | 27 | 2010 |
| Correction of delay-based metric measurements using delay circuits having differing metric sensitivities H Singh, AJ Drake, FH Gebara, JP Keane, JD Schaub, RM Senger US Patent 7,548,823, 2009 | 23 | 2009 |
| A 0.094 um 2 high density and aging resilient 8T SRAM with 14nm FinFET technology featuring 560mV VMIN with read and write assist KH Koo, L Wei, J Keane, U Bhattacharya, E Karl, K Zhang IEEE Symposium on VLSI Circuits, 2015 | 21 | 2015 |
| Delay-based bias temperature instability recovery measurements for characterizing stress degradation and recovery FH Gebara, JD Hayes, JP Keane, SR Nassif, JD Schaub US Patent 7,949,482, 2011 | 18 | 2011 |
| Test circuit for bias temperature instability recovery measurements FH Gebara, JD Hayes, JP Keane, SR Nassif, JD Schaub US Patent 8,229,683, 2012 | 13 | 2012 |
| Sleep transistor sizing and adaptive control for supply noise minimization considering resonance J Gu, H Eom, J Keane, CH Kim IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 1203-1211, 2009 | 10 | 2009 |