Следене
Javad Talafy Daryani
Заглавие
Позовавания
Позовавания
Година
Soft error analysis of MTJ-based logic-in-memory full adder: Threats and solution
J Talafy, HR Zarandi
International Symposium on On-Line Testing and Robust System Design (IOLTS …, 2017
102017
DUSTER: Dual source write termination method for STT-RAM memories
SS Faraji, J Talafy, AM Hajisadeghi, HR Zarandi
2018 21st Euromicro Conference on Digital System Design (DSD), 182-189, 2018
82018
EXTENT: Enabling approximation-oriented energy efficient STT-RAM write circuit
S Seyedfaraji, JT Daryani, MMS Aly, S Rehman
IEEE Access 10, 82144-82155, 2022
72022
A High Performance, Multi-Bit Output Logic-in-Memory Adder
J Talafy, F Zokaie, HR Zarandi, N Bagherzadeh
IEEE Transactions on Emerging Topics in Computing (TETC), 2020
72020
DYSCO: DYnamic Stepper Current InjectOr to improve write performance in STT-RAM memories
S Seyedfaraji, AM Hajisadeghi, J Talafy, HR Zarandi
Microprocessors and Microsystems (MICPRO) 73, 102963, 2020
72020
Nanoscale memristive devices: Threats and solutions
AM Hajisadeghi, J Talafy, HR Zarandi
Nanoscale Memristor Device and Circuits Design, 137-163, 2024
2024
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