A calibration-free fractional-N ring PLL using hybrid phase/current-mode phase interpolation method RK Nandwana, T Anand, S Saxena, SJ Kim, M Talegaonkar, A Elkholy, ...
IEEE Journal of Solid-State Circuits 50 (4), 882-895, 2015
85 2015 A 2.0–5.5 GHz Wide Bandwidth Ring-Based Digital Fractional-N PLL With Extended Range Multi-Modulus Divider A Elkholy, S Saxena, RK Nandwana, A Elshazly, PK Hanumolu
IEEE Journal of Solid-State Circuits 51 (8), 1771-1784, 2016
78 2016 A Process and Temperature Insensitive CMOS Linear TIA for 100 Gb/s/ KR Lakshmikumar, A Kurylak, M Nagaraju, R Booth, RK Nandwana, ...
IEEE Journal of Solid-State Circuits 54 (11), 3180-3190, 2019
77 2019 A 4-Phase 30–70 MHz Switching Frequency Buck Converter Using a Time-Based Compensator SJ Kim, RK Nandwana, Q Khan, RCN Pilawa-Podgurski, PK Hanumolu
IEEE Journal of Solid-State Circuits 50 (12), 2814-2824, 2015
70 2015 8.6 A 2.5-to-5.75GHz 5mW 0.3psrms -jitter cascaded ring-based digital injection-locked clock multiplier in 65nm CMOS D Coombs, A Elkholy, RK Nandwana, A Elmallah, PK Hanumolu
2017 IEEE International Solid-State Circuits Conference (ISSCC), 152-153, 2017
60 2017 A 2.5–5.75-GHz Ring-Based Injection-Locked Clock Multiplier With Background-Calibrated Reference Frequency Doubler A Elkholy, D Coombs, RK Nandwana, A Elmallah, PK Hanumolu
IEEE Journal of Solid-State Circuits 54 (7), 2049-2058, 2019
54 2019 A 0.0021 mm2 1.82 mW 2.2 GHz PLL Using Time-Based Integral Control in 65 nm CMOS J Zhu, RK Nandwana, G Shu, A Elkholy, SJ Kim, PK Hanumolu
IEEE Journal of Solid-State Circuits 52 (1), 8-20, 2017
50 2017 A 5 Gb/s Energy-Efficient Voltage-Mode Transmitter Using Time-Based De-Emphasis S Saxena, RK Nandwana, PK Hanumolu
IEEE Journal of Solid-State Circuits 49 (8), 1827-1836, 2014
42 2014 12.2 A1.8V 30-to-70MHz 87% peak-efficiency 0.32mm2 4-phase time-based buck converter consuming 3μA/MHz quiescent current in 65nm CMOS SJ Kim, RK Nandwana, Q Khan, R Pilawa-Podgurski, PK Hanumolu
2015 IEEE International Solid-State Circuits Conference-(ISSCC) Digest of …, 2015
27 2015 A 2.8 mW/Gb/s, 14 Gb/s serial link transceiver S Saxena, G Shu, RK Nandwana, M Talegaonkar, A Elkholy, T Anand, ...
IEEE Journal of Solid-State Circuits 52 (5), 1399-1411, 2017
24 2017 A 16-Gb/s-11.6-dBm OMA Sensitivity 0.7-pJ/bit Optical Receiver in 65-nm CMOS Enabled by Duobinary Sampling MG Ahmed, D Kim, RK Nandwana, A Elkholy, KR Lakshmikumar, ...
IEEE Journal of Solid-State Circuits 56 (9), 2795-2803, 2021
21 2021 Digital fractional-N multiplying injection locked oscillator RK Nandwana, P Upadhyaya
US Patent 9,614,537, 2017
19 2017 23.1 a 16mb/s-to-8gb/s 14.1-to-5.9 pj/b source synchronous transceiver using dvfs and rapid on/off in 65nm cmos G Shu, WS Choi, S Saxena, SJ Kim, M Talegaonkar, R Nandwana, ...
2016 IEEE International Solid-State Circuits Conference (ISSCC), 398-399, 2016
16 2016 A 4.4–5.4 GHz digital fractional-N PLL using ΔΣ frequency-to-digital converter M Talegaonkar, T Anand, A Elkholy, A Elshazly, RK Nandwana, S Saxena, ...
2014 Symposium on VLSI Circuits Digest of Technical Papers, 1-2, 2014
16 2014 A 2.8 mW/Gb/s 14Gb/s serial link transceiver in 65nm CMOS S Saxena, G Shu, RK Nandwana, M Talegaonkar, A Elkholy, T Anand, ...
2015 Symposium on VLSI Circuits (VLSI Circuits), C352-C353, 2015
15 2015 29.6 a 3-to-10Gb/s 5.75 pJ/b transceiver with flexible clocking in 65nm CMOS RK Nandwana, S Saxena, A Elkholy, M Talegaonkar, J Zhu, WS Choi, ...
2017 IEEE International Solid-State Circuits Conference (ISSCC), 492-493, 2017
14 2017 A 1-to-2048 Fully-Integrated Cascaded Digital Frequency Synthesizer for Low Frequency Reference Clocks Using Scrambling TDC RK Nandwana, S Saxena, A Elshazly, K Mayaram, PK Hanumolu
IEEE Transactions on Circuits and Systems I: Regular Papers 64 (2), 283-295, 2017
13 2017 A 7 pA/ K Lakshmikumar, A Kurylak, RK Nandwana, B Das, J Pampanin, ...
2023 IEEE International Solid-State Circuits Conference (ISSCC), 206-208, 2023
11 2023 A 5GHz Digital Fractional- M Talegaonkar, T Anand, A Elkholy, A Elshazly, RK Nandwana, S Saxena, ...
IEEE Journal of Solid-State Circuits 52 (9), 2306-2320, 2017
10 2017 A 4.25 GHz–4.75 GHz calibration-free fractional-N ring PLL using hybrid phase/current-mode phase interpolator with 13.2 dB phase noise improvement RK Nandwana, T Anand, S Saxena, SJ Kim, M Talegaonkar, A Elkholy, ...
2014 Symposium on VLSI Circuits Digest of Technical Papers, 1-2, 2014
9 2014 
Saurabh SaxenaAssociate Professor, Indian Institute of Technology MadrasПотвърден имейл адрес: ee.iitm.ac.in
