Следене
Abhishek Bhat
Abhishek Bhat
ASIC Engineering Technical Leader at Cisco Systems Inc.
Потвърден имейл адрес: cisco.com - Начална страница
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Позовавания
Позовавания
Година
26.3 A 25-to-38GHz, 195dB FoMT LC QVCO in 65nm LP CMOS using a 4-port dual-mode resonator for 5G radios
A Bhat, N Krishnapura
2019 IEEE International Solid-State Circuits Conference-(ISSCC), 412-414, 2019
692019
LowPhase Noise Quadrature LC VCOs
A Bhat, N Krishnapura
IEEE Transactions on Circuits and Systems I: Regular Papers 65 (7), 2127-2138, 2018
272018
A Reduced-Area Capacitor-Only Loop Filter With Polarity-Switched Gₘ for Large Multiplication Factor Millimeter-Wave Sub-Sampling PLLs
A Bhat, N Krishnapura
IEEE Transactions on Circuits and Systems I: Regular Papers, 2021
92021
Low Power Portable EEG for Continuous Monitoring with Active Electrodes
B Abhishek, AG Poojary, MVA Rao, S Narayanan
2013 Texas Instruments India Educators' Conference, 332-339, 2013
62013
Frequency tracking loop using a scaled replica oscillator for injection locked oscillators
A Bhat, RK Nandwana, K Lakshmikumar, PK Hanumolu
US Patent 11,356,107, 2022
42022
An Interference Suppression Technique for Millimeter-Wave LC VCOs using a Multiport Coupled Inductor
A Bhat, R Nandwana, K Lakshmikumar
IEEE Transactions on Circuits and Systems II: Express Briefs, 1 - 1, 2021
42021
A tail-resonance calibration technique for wide tuning range LC VCOs
A Bhat, N Krishnapura
2016 IEEE International Symposium on Circuits and Systems (ISCAS), 2070-2073, 2016
42016
On-chip static phase difference measurement circuit with gain and offset calibration
A Bhat, N Krishnapura
IEEE Transactions on Circuits and Systems II: Express Briefs 66 (2), 162-166, 2018
32018
A 6 to 12-GHz Fractional- Frequency Synthesizer With a Digital Technique to Counter Modulus-Dependent Feedback Divider Delays
A Narayanan, A Bhat, N Krishnapura
IEEE Journal of Solid-State Circuits, 2024
22024
Phase-locked loop with phase noise cancellation
A Bhat, RK Nandwana
US Patent 11,398,827, 2022
22022
Hybrid fractional-N sampling phase locked loop (PLL) with accurate digital-to-time converter (DTC) calibration
A Bhat, RK Nandwana, PK Hanumolu, K Lakshmikumar
US Patent 11,901,906, 2024
12024
Dual-core dual-resonance compact inductor-capacitor voltage controlled oscillator
A Bhat, RK Nandwana, K Lakshmikumar
US Patent 11,218,113, 2022
12022
INDUCTIVE-CAPACITIVE VOLTAGE-CONTROLLED OSCILLATOR WITH INCREASED COMMON-MODE IMPEDANCE
A Bhat, JV Pampanin
US Patent App. 18/456,373, 2025
2025
Clock jitter and spurious tone cancellation system using optical delay
A Bhat, SH RAMACHANDRA
US Patent 12,191,870, 2025
2025
LOCAL SILICON-PHOTONICS TEMPERATURE SENSOR
S Handanhal Ramachandra, A Bhat, PM Kasturi
US Patent App. 18/341,543, 2024
2024
Segmented digital-to-time converter
A Bhat, A Bharadwaj, RK Nandwana
US Patent 12,147,201, 2024
2024
Latch-up mitigated charge pump for high power supply rejection low-dropout regulator
BP Das, A Bhat, K Lakshmikumar, RK Nandwana
US Patent App. 18/299,174, 2024
2024
Low area equalizer with lane mismatch adaptation for sub-rate receivers
RK Nandwana, A Bhat, K Lakshmikumar, PK Hanumolu
US Patent 11,863,222, 2024
2024
Calibration loop for differential sub-sampling phase detector in sub-sampling phase locked loop
A Bhat, RK Nandwana
US Patent 11,716,087, 2023
2023
Frequency tracking loop using a scaled replica oscillator for injection locked oscillators
A Bhat, RK Nandwana, K Lakshmikumar, PK Hanumolu
US Patent 11,671,105, 2023
2023
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