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Arash Ardakani
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VLSI implementation of deep neural network using integral stochastic computing
A Ardakani, F Leduc-Primeau, N Onizawa, T Hanyu, WJ Gross
IEEE Transactions on Very Large Scale Integration (VLSI) Systems 25 (10 …, 2017
3042017
An architecture to accelerate convolution in deep neural networks
A Ardakani, C Condo, M Ahmadi, WJ Gross
IEEE Transactions on Circuits and Systems I: Regular Papers 65 (4), 1349-1362, 2017
1452017
Sparsely-connected neural networks: towards efficient VLSI implementation of deep neural networks
A Ardakani, C Condo, WJ Gross
International Conference on Learning Representations (ICLR) 2017, 2017
1222017
Fast and efficient convolutional accelerator for edge computing
A Ardakani, C Condo, WJ Gross
IEEE Transactions on Computers 69 (1), 138-152, 2019
542019
Stochastic computing can improve upon digital spiking neural networks
SC Smithson, K Boga, A Ardakani, BH Meyer, WJ Gross
2016 IEEE International Workshop on Signal Processing Systems (SiPS), 309-314, 2016
442016
Learning Recurrent Binary/Ternary Weights
A Ardakani, Z Ji, SC Smithson, BH Meyer, WJ Gross
International Conference on Learning Representations (ICLR) 2019, 2019
362019
Design and implementation of a polar codes blind detection scheme
C Condo, SA Hashemi, A Ardakani, F Ercan, WJ Gross
IEEE Transactions on Circuits and Systems II: Express Briefs 66 (6), 943-947, 2018
362018
Hardware implementation of FIR/IIR digital filters using integral stochastic computation
A Ardakani, F Leduc-Primeau, WJ Gross
2016 IEEE International Conference on Acoustics, Speech and Signal …, 2016
252016
An efficient VLSI architecture of QPP interleaver/deinterleaver for LTE turbo coding
A Ardakani, M Mahdavi, M Shabany
2013 IEEE International Symposium on Circuits and Systems (ISCAS), 797-800, 2013
222013
A convolutional accelerator for neural networks with binary weights
A Ardakani, C Condo, WJ Gross
2018 IEEE International Symposium on Circuits and Systems (ISCAS), 1-5, 2018
192018
Learning to Skip Ineffectual Recurrent Computations in LSTMs
A Ardakani, Z Ji, WJ Gross
Design, Automation & Test in Europe Conference & Exhibition (DATE), 2019, 2019
172019
A novel area-efficient VLSI architecture for recursion computation in LTE turbo decoders
A Ardakani, M Shabany
IEEE Transactions on Circuits and Systems II: Express Briefs 62 (6), 568-572, 2015
172015
Activation pruning of deep convolutional neural networks
A Ardakani, C Condo, WJ Gross
2017 IEEE Global Conference on Signal and Information Processing (GlobalSIP …, 2017
162017
The synthesis of XNOR recurrent neural networks with stochastic logic
A Ardakani, Z Ji, A Ardakani, W Gross
Advances in Neural Information Processing Systems 32, 2019
152019
The vital role of pistachio processing industries in development of Iran non-oil exports
ASH Ardakani
IV International Symposium on Pistachios and Almonds 726, 579-582, 2005
152005
Optimizing of the process of pistachio butter production
AS Ardakani, M Shahedi, G Kabir
IV International Symposium on Pistachios and Almonds 726, 565-568, 2005
152005
Optimizing formulation of pistachio butter production.
AS Ardakani, M Shahedi, G Kabir
122009
Hardware-aware design for edge intelligence
WJ Gross, BH Meyer, A Ardakani
IEEE Open Journal of Circuits and Systems 2, 113-127, 2020
92020
An efficient max-log map algorithm for vlsi implementation of turbo decoders
A Ardakani, M Shabany
2015 IEEE International Symposium on Circuits and Systems (ISCAS), 1794-1797, 2015
92015
Training linear finite-state machines
A Ardakani, A Ardakani, W Gross
Advances in Neural Information Processing Systems 33, 7173-7183, 2020
82020
En aquests moments el sistema no pot dur a terme l'operació. Torneu-ho a provar més tard.
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