| 24.4 sandwich-RAM: An energy-efficient in-memory BWN architecture with pulse-width modulation J Yang, Y Kong, Z Wang, Y Liu, B Wang, S Yin, L Shi 2019 IEEE International Solid-State Circuits Conference-(ISSCC), 394-396, 2019 | 148 | 2019 |
| A 28-nm 64-kb 31.6-TFLOPS/W Digital-Domain Floating-Point-Computing-Unit and Double-Bit 6T-SRAM Computing-in-Memory Macro for Floating-Point CNNs A Guo, X Chen, F Dong, X Pu, D Li, J Zhang, X Dong, H Gao, Y Zhang, ... IEEE Journal of Solid-State Circuits, 2024 | 59 | 2024 |
| A 28nm horizontal-weight-shift and vertical-feature-shift-based separate-WL 6T-SRAM computation-in-memory unit-macro for edge depthwise neural-networks B Wang, C Xue, Z Feng, Z Zhang, H Liu, L Ren, X Li, A Yin, T Xiong, ... 2023 IEEE International Solid-State Circuits Conference (ISSCC), 134-136, 2023 | 32 | 2023 |
| TIMAQ: A time-domain computing-in-memory-based processor using predictable decomposed convolution for arbitrary quantized DNNs J Yang, Y Kong, Z Zhang, Z Liu, J Zhou, Y Wang, Y Liu, C Guo, T Hu, C Li, ... IEEE Journal of Solid-State Circuits 56 (10), 3021-3038, 2021 | 23 | 2021 |
| From macro to microarchitecture: Reviews and trends of SRAM-based compute-in-memory circuits Z Zhang, J Chen, X Chen, A Guo, B Wang, T Xiong, Y Kong, X Pu, S He, ... Science China Information Sciences 66 (10), 200403, 2023 | 10 | 2023 |
| Evaluation platform of time-domain computing-in-memory circuits Y Kong, X Chen, X Si, J Yang IEEE Transactions on Circuits and Systems II: Express Briefs 70 (3), 1174-1178, 2022 | 10 | 2022 |
| SNNIM: A 10T-SRAM based Spiking-Neural-Network-In-Memory architecture with capacitance computation B Wang, C Xue, H Liu, X Li, A Yin, Z Feng, Y Kong, T Xiong, H Hsu, ... 2022 IEEE International Symposium on Circuits and Systems (ISCAS), 3383-3387, 2022 | 9 | 2022 |
| Design challenges and methodology of high-performance SRAM-based compute-in-memory for AI edge devices Y Wang, Y Zhou, B Wang, T Xiong, Y Kong, X Si 2021 International Conference on UK-China Emerging Technologies (UCET), 47-52, 2021 | 7 | 2021 |
| Design methodology towards high-precision SRAM based computation-in-memory for AI edge devices T Xiong, Y Zhou, Y Kong, B Wang, A Guo, Y Wang, C Xue, H Hsu, X Si, ... 2021 18th International SoC Design Conference (ISOCC), 195-196, 2021 | 5 | 2021 |
| A time-domain computing-in-memory based processor using predictable decomposed convolution for arbitrary quantized DNNs J Yang, Y Kong, Z Zhang, Z Liu, J Zhou, Y Wang, Y Liu, C Guo, T Hu, C Li, ... 2020 IEEE Asian Solid-State Circuits Conference (A-SSCC), 1-4, 2020 | 5 | 2020 |
| Toggle rate aware quantization model based on digital floating-point computing-in-memory architecture X Chen, Y Zhao, A Guo, J Chen, F Dong, Z Zhang, T Xiong, B Wang, ... IEEE Transactions on Circuits and Systems II: Express Briefs 71 (6), 3181-3185, 2024 | 2 | 2024 |
| DATIC: A Data-Aware Time-Domain Computing-in-Memory-Based CNN Processor with Dynamic Channel Skipping and Mapping J Yang, Y Kong, Y Li, C Guo, H Sun, L Liu, S Wei, J Yang, S Yin IEEE Open Journal of the Solid-State Circuits Society 2, 244-258, 2022 | 1 | 2022 |
| A time-domain compute-in-memory architecture based on pulse width modulation for multi-bits convolutional neural networks Y Kong, X Si Authorea Preprints, 2023 | | 2023 |
| In-memory Processing based on Time-domain Circuit Y Kong, J Yang Proceedings of the 2019 Great Lakes Symposium on VLSI, 435-438, 2019 | | 2019 |
