| Flexflow: A flexible dataflow accelerator architecture for convolutional neural networks W Lu, G Yan, J Li, S Gong, Y Han, X Li 2017 IEEE International Symposium on High Performance Computer Architecture …, 2017 | 429 | 2017 |
| SmartShuttle: Optimizing off-chip memory accesses for deep learning accelerators J Li, G Yan, W Lu, S Jiang, S Gong, J Wu, X Li 2018 Design, Automation & Test in Europe Conference & Exhibition (DATE), 343-348, 2018 | 119 | 2018 |
| AxTrain: Hardware-oriented neural network training for approximate inference X He, L Ke, W Lu, G Yan, X Zhang Proceedings of the International Symposium on Low Power Electronics and …, 2018 | 42 | 2018 |
| Joint design of training and hardware towards efficient and accuracy-scalable neural network inference X He, W Lu, G Yan, X Zhang IEEE Journal on Emerging and Selected Topics in Circuits and Systems 8 (4 …, 2018 | 26 | 2018 |
| Exploiting the potential of computation reuse through approximate computing X He, S Jiang, W Lu, G Yan, Y Han, X Li IEEE Transactions on Multi-Scale Computing Systems 3 (3), 152-165, 2016 | 23 | 2016 |
| TNPU: an efficient accelerator architecture for training convolutional neural networks J Li, G Yan, W Lu, S Jiang, S Gong, J Wu, J Yan, X Li Proceedings of the 24th Asia and South Pacific Design Automation Conference …, 2019 | 16 | 2019 |
| CCR: A concise convolution rule for sparse neural network accelerators J Li, G Yan, W Lu, S Jiang, S Gong, J Wu, X Li 2018 Design, Automation & Test in Europe Conference & Exhibition (DATE), 189-194, 2018 | 11 | 2018 |
| ShuntFlow: An Efficient and Scalable Dataflow Accelerator Architecture for Streaming Applications S Gong, J Li, W Lu, G Yan, X Li Proceedings of the 56th Annual Design Automation Conference 2019, 194, 2019 | 7 | 2019 |
| Promoting the Harmony between Sparsity and Regularity: A Relaxed Synchronous Architecture for Convolutional Neural Networks W Lu, G Yan, J Li, S Gong, S Jiang, J Wu, X Li IEEE Transactions on Computers 68 (6), 867-881, 2018 | 5 | 2018 |
| SynergyFlow: An Elastic Accelerator Architecture Supporting Batch Processing of Large-Scale Deep Neural Networks J Li, G Yan, W Lu, S Gong, S Jiang, J Wu, X Li ACM Transactions on Design Automation of Electronic Systems (TODAES) 24 (1), 8, 2018 | 5 | 2018 |
| Leveraging PVT-Margins in Design Space Exploration for FPGA-based CNN Accelerators W Lu, W Lu, J Ye, Y Hu, X Li 2017 27th International Conference on Field Programmable Logic and …, 2017 | 3 | 2017 |
| A Quantitative Exploration of Collaborative Pruning and Approximation Towards Energy-Efficient Deep Neural Networks X He, W Lu, K Liu, G Yan, X Zhang IEEE Design & Test, 2019 | 2 | 2019 |
| AdaFlow: Aggressive Convolutional Neural Networks Approximation by Leveraging the Input Variability W Lu, G Yan, X Li Journal of Low Power Electronics 14 (4), 481-495, 2018 | 2 | 2018 |
| MLA: Machine Learning Adaptation for Realtime Streaming Financial Applications J Wu, W Lu, G Yan, X Li | 2* | |
