| FP-BNN: Binarized neural network on FPGA S Liang, S Yin, L Liu, W Luk, S Wei Neurocomputing 275, 1072-1086, 2018 | 363 | 2018 |
| Deep convolutional neural network architecture with reconfigurable computation patterns F Tu, S Yin, P Ouyang, S Tang, L Liu, S Wei IEEE Transactions on Very Large Scale Integration (VLSI) Systems 25 (8 …, 2017 | 355 | 2017 |
| A survey of coarse-grained reconfigurable architecture and design: Taxonomy, challenges, and applications L Liu, J Zhu, Z Li, Y Lu, Y Deng, J Han, S Yin, S Wei ACM Computing Surveys (CSUR) 52 (6), 1-39, 2019 | 234 | 2019 |
| A high energy efficient reconfigurable hybrid neural network processor for deep learning applications S Yin, P Ouyang, S Tang, F Tu, X Li, S Zheng, T Lu, J Gu, L Liu, S Wei IEEE Journal of Solid-State Circuits 53 (4), 968-982, 2017 | 226 | 2017 |
| A crop monitoring system based on wireless sensor network Z Liqiang, Y Shouyi, L Leibo, Z Zhen, W Shaojun Procedia Environmental Sciences 11, 558-565, 2011 | 197 | 2011 |
| Highly efficient architecture of NewHope-NIST on FPGA using low-complexity NTT/INTT N Zhang, B Yang, C Chen, S Yin, S Wei, L Liu IACR Transactions on Cryptographic Hardware and Embedded Systems, 49-72, 2020 | 169 | 2020 |
| Efficient hardware architecture of softmax layer in deep neural network R Hu, B Tian, S Yin, S Wei 2018 IEEE 23rd International Conference on Digital Signal Processing (DSP), 1-5, 2018 | 152 | 2018 |
| 24.4 sandwich-RAM: An energy-efficient in-memory BWN architecture with pulse-width modulation J Yang, Y Kong, Z Wang, Y Liu, B Wang, S Yin, L Shi 2019 IEEE International Solid-State Circuits Conference-(ISSCC), 394-396, 2019 | 148 | 2019 |
| A 5.1 pJ/neuron 127.3 us/inference RNN-based speech recognition processor using 16 computing-in-memory SRAM macros in 65nm CMOS R Guo, Y Liu, S Zheng, SY Wu, P Ouyang, WS Khwa, X Chen, JJ Chen, ... 2019 Symposium on VLSI Circuits, C120-C121, 2019 | 113 | 2019 |
| Traffic-aware routing in wireless networks YQ Xiong, Q Zhang, S Yin US Patent 7,660,285, 2010 | 110 | 2010 |
| A multilevel cell STT-MRAM-based computing in-memory accelerator for binary convolutional neural network Y Pan, P Ouyang, Y Zhao, W Kang, S Yin, Y Zhang, W Zhao, S Wei IEEE Transactions on Magnetics 54 (11), 1-5, 2018 | 109 | 2018 |
| A 1.06-to-5.09 TOPS/W reconfigurable hybrid-neural-network processor for deep learning applications S Yin, P Ouyang, S Tang, F Tu, X Li, L Liu, S Wei 2017 Symposium on VLSI Circuits, C26-C27, 2017 | 107 | 2017 |
| A 28nm 29.2 TFLOPS/W BF16 and 36.5 TOPS/W INT8 reconfigurable digital CIM processor with unified FP/INT pipeline and bitwise in-memory booth multiplication for cloud deep … F Tu, Y Wang, Z Wu, L Liang, Y Ding, B Kim, L Liu, S Wei, Y Xie, S Yin 2022 IEEE International Solid-State Circuits Conference (ISSCC) 65, 1-3, 2022 | 95 | 2022 |
| RANA: Towards efficient neural acceleration with refresh-optimized embedded DRAM F Tu, W Wu, S Yin, L Liu, S Wei 2018 ACM/IEEE 45th Annual International Symposium on Computer Architecture …, 2018 | 85 | 2018 |
| A 141 uw, 2.46 pj/neuron binarized convolutional neural network based self-learning speech recognition processor in 28nm cmos S Yin, P Ouyang, S Zheng, D Song, X Li, L Liu, S Wei 2018 IEEE Symposium on VLSI Circuits, 139-140, 2018 | 83 | 2018 |
| Polyhedral model based mapping optimization of loop nests for CGRAs D Liu, S Yin, L Liu, S Wei Proceedings of the 50th Annual Design Automation Conference, 1-8, 2013 | 83 | 2013 |
| Fast traffic sign recognition with a rotation invariant binary pattern based feature S Yin, P Ouyang, L Liu, Y Guo, S Wei Sensors 15 (1), 2161-2180, 2015 | 69 | 2015 |
| Energy Efficient Beamforming Design Ior Multi-Carrier Multi-user Systems with Nonlinear Amplifiers Z Wang, L Vandendorpe 2018 15th International Symposium on Wireless Communication Systems (ISWCS), 1-5, 2018 | 64 | 2018 |
| An energy-efficient reconfigurable processor for binary-and ternary-weight neural networks with flexible data bit width S Yin, P Ouyang, J Yang, T Lu, X Li, L Liu, S Wei IEEE Journal of Solid-State Circuits 54 (4), 1120-1136, 2018 | 62 | 2018 |
| An ultra-low power binarized convolutional neural network-based speech recognition processor with on-chip self-learning S Zheng, P Ouyang, D Song, X Li, L Liu, S Wei, S Yin IEEE Transactions on Circuits and Systems I: Regular Papers 66 (12), 4648-4661, 2019 | 61 | 2019 |
