| Slack redistribution for graceful degradation under voltage overscaling AB Kahng, S Kang, R Kumar, J Sartori 2010 15th Asia and South Pacific Design Automation Conference (ASP-DAC), 825-831, 2010 | 227 | 2010 |
| Scalable stochastic processors S Narayanan, J Sartori, R Kumar, DL Jones 2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010 …, 2010 | 191 | 2010 |
| Designing a processor from the ground up to allow voltage/reliability tradeoffs AB Kahng, S Kang, R Kumar, J Sartori HPCA-16 2010 The Sixteenth International Symposium on High-Performance …, 2010 | 140 | 2010 |
| Branch and data herding: Reducing control and memory divergence for error-tolerant GPU applications J Sartori, R Kumar Proceedings of the 21st international conference on Parallel architectures …, 2012 | 120 | 2012 |
| On the efficacy of NBTI mitigation techniques TB Chan, J Sartori, P Gupta, R Kumar 2011 Design, Automation & Test in Europe, 1-6, 2011 | 85 | 2011 |
| Statistical analysis and modeling for error composition in approximate computation circuits WTJ Chan, AB Kahng, S Kang, R Kumar, J Sartori 2013 IEEE 31st international conference on computer design (ICCD), 47-53, 2013 | 83 | 2013 |
| Low-power, low-storage-overhead chipkill correct via multi-line error correction X Jian, H Duwe, J Sartori, V Sridharan, R Kumar Proceedings of the International Conference on High Performance Computing …, 2013 | 77 | 2013 |
| Approximate communication: Techniques for reducing communication bottlenecks in large-scale parallel systems F Betzel, K Khatamifard, H Suresh, DJ Lilja, J Sartori, U Karpuzcu ACM Computing Surveys (CSUR) 51 (1), 1-32, 2018 | 74 | 2018 |
| Recovery-driven design: A power minimization methodology for error-tolerant processor modules AB Kahng, S Kang, R Kumar, J Sartori Proceedings of the 47th Design Automation Conference, 825-830, 2010 | 68 | 2010 |
| Distributed peak power management for many-core architectures J Sartori, R Kumar 2009 Design, Automation & Test in Europe Conference & Exhibition, 1556-1559, 2009 | 67 | 2009 |
| Stochastic computing: embracing errors in architectureand design of processors and applications J Sartori, J Sloan, R Kumar Proceedings of the 14th international conference on compilers, architectures …, 2011 | 66 | 2011 |
| Low-overhead, high-speed multi-core barrier synchronization J Sartori, R Kumar International Conference on High-Performance Embedded Architectures and …, 2010 | 65 | 2010 |
| Designing a cost-effective cache replacement policy using machine learning S Sethumurugan, J Yin, J Sartori 2021 IEEE International Symposium on High-Performance Computer Architecture …, 2021 | 61 | 2021 |
| Exploiting dynamic timing slack for energy efficiency in ultra-low-power embedded systems H Cherupalli, R Kumar, J Sartori ACM SIGARCH Computer Architecture News 44 (3), 671-681, 2016 | 60 | 2016 |
| Power balanced pipelines J Sartori, B Ahrens, R Kumar IEEE International Symposium on High-Performance Comp Architecture, 1-12, 2012 | 56 | 2012 |
| Enhancing the efficiency of energy-constrained DVFS designs AB Kahng, S Kang, R Kumar, J Sartori IEEE Transactions on Very Large Scale Integration (VLSI) Systems 21 (10 …, 2012 | 50 | 2012 |
| Variation-aware speed binning of multi-core processors J Sartori, A Pant, R Kumar, P Gupta 2010 11th International Symposium on Quality Electronic Design (ISQED), 307-314, 2010 | 48 | 2010 |
| Bespoke processors for applications with ultra-low area and power constraints H Cherupalli, H Duwe, W Ye, R Kumar, J Sartori Proceedings of the 44th Annual International Symposium on Computer …, 2017 | 40 | 2017 |
| Determining application-specific peak power and energy requirements for ultra-low-power processors H Cherupalli, H Duwe, W Ye, R Kumar, J Sartori ACM Transactions on Computer Systems (TOCS) 35 (3), 1-33, 2017 | 35 | 2017 |
| Power balanced pipelines R Kumar, BJ Ahrens, JM Sartori US Patent 8,806,410, 2014 | 33 | 2014 |
