A 90-nm logic technology featuring strained-silicon SE Thompson, M Armstrong, C Auth, M Alavi, M Buehler, R Chau, S Cea, ...
IEEE Transactions on electron devices 51 (11), 1790-1797, 2004
952 2004 A 90 nm logic technology featuring 50 nm strained silicon channel transistors, 7 layers of Cu interconnects, low k ILD, and 1/spl mu/m/sup 2/SRAM cell S Thompson, N Anand, M Armstrong, C Auth, B Arcot, M Alavi, P Bai, ...
Digest. International Electron Devices Meeting,, 61-64, 2002
458 2002 A 22nm SoC platform technology featuring 3-D tri-gate and high-k/metal gate, optimized for ultra low power, high performance and high density SoC applications CH Jan, U Bhattacharya, R Brain, SJ Choi, G Curello, G Gupta, W Hafez, ...
2012 International Electron Devices Meeting, 3.1. 1-3.1. 4, 2012
378 2012 A 32nm SoC platform technology with 2nd generation high-k/metal gate transistors optimized for ultra low power, high performance, and high density product … CH Jan, M Agostinelli, M Buehler, ZP Chen, SJ Choi, G Curello, ...
2009 IEEE International Electron Devices Meeting (IEDM), 1-4, 2009
370 2009 IEEE International Electron Devices Meeting (IEDM) CH Jan, M Agostinelli, M Buehler, ZP Chen, SJ Choi, G Curello, ...
San Francisco, USA, 3.1, 2012
347 2012 Non-planar semiconductor device having omega-fin with doped sub-fin region and method to fabricate same G Bhimarasetti, WM Hafez, J Park, W Han, RE Cotner, CH Jan
US Patent 10,355,093, 2019
294 2019 Device structure and method for reducing silicide encroachment RS Chau, E Andideh, MC Taylor, CH Jan, J Tsai
US Patent 6,765,273, 2004
236 2004 Method of forming a transistor RS Chau, CH Jan, P Packan, MC Taylor
US Patent 5,908,313, 1999
217 1999 Semiconductor device having deposited silicon regions and a method of fabrication A Murthy, CH Jan, E Andideh, K Weldon
US Patent 6,235,568, 2001
212 2001 Transistor with low resistance tip and method of fabrication in a CMOS process RS Chau, CH Jan, CH Chern, LD Yau
US Patent 6,165,826, 2000
200 2000 Memory cell using BTI effects in high-k metal gate MOS WM Hafez, A Rahman, CH Jan
US Patent 8,432,751, 2013
179 2013 Device having thin first spacers and partially recessed thick second spacers for improved salicide resistance on polysilicon gates CH Jan, JA Tsai, S Yang, T Ghani, KA Whitehill, SJ Keating, A Myers
US Patent 6,509,618, 2003
147 2003 Device having spacers for improved salicide resistance on polysilicon gates CH Jan, JA Tsai, S Yang, T Ghani, KA Whitehill, SJ Keating, A Myers
US Patent 6,521,964, 2003
146 2003 Method of recessing spacers to improved salicide resistance on polysilicon gates CH Jan, JA Tsai, S Yang, T Ghani, KA Whitehill, SJ Keating, A Myers
US Patent 6,506,652, 2003
145 2003 Transistor with ultra shallow tip and method of fabrication RS Chau, CH Chern, CH Jan, KR Weldon, PA Packan, LD Yau
US Patent 5,710,450, 1998
144 1998 A 1.1 GHz 12 Y Wang, HJ Ahn, U Bhattacharya, Z Chen, T Coan, F Hamzaoglu, ...
IEEE Journal of Solid-State Circuits 43 (1), 172-179, 2008
138 2008 Self-heat reliability considerations on Intel's 22nm Tri-Gate technology C Prasad, L Jiang, D Singh, M Agostinelli, C Auth, P Bai, T Eiles, J Hicks, ...
2013 IEEE International Reliability Physics Symposium (IRPS), 5D. 1.1-5D. 1.5, 2013
124 2013 RF CMOS technology scaling in high-k/metal gate era for RF SoC (system-on-chip) applications CH Jan, M Agostinelli, H Deshpande, MA El-Tanani, W Hafez, U Jalan, ...
2010 international electron devices meeting, 27.2. 1-27.2. 4, 2010
119 2010 Method of fabricating a field effect transistor structure with abrupt source/drain junctions AS Murthy, RS Chau, P Morrow, CH Jan, P Packan
US Patent 6,887,762, 2005
115 2005 A high performance 180 nm generation logic technology S Yang, S Ahmed, B Arcot, R Arghavani, P Bai, S Chambers, P Charvat, ...
International Electron Devices Meeting 1998. Technical Digest (Cat. No …, 1998
113 1998 