| Hardware Trojan insertion by direct modification of FPGA configuration bitstream RS Chakraborty, I Saha, A Palchaudhuri, GK Naik Design & Test, IEEE 30 (2), 45-54, 2013 | 198 | 2013 |
| High Performance Integer Arithmetic Circuit Design on FPGA A Palchaudhuri, RS Chakraborty Springer India, 2016 | 27 | 2016 |
| Efficient implementation of scan register insertion on integer arithmetic cores for FPGAs A Palchaudhuri, AS Dhar 2016 29th International Conference on VLSI Design and 2016 15th …, 2016 | 18 | 2016 |
| Built-in fault localization circuitry for high performance FPGA based implementations A Palchaudhuri, AS Dhar Journal of Electronic Testing 33, 529-537, 2017 | 15 | 2017 |
| Design and automation of VLSI architectures for bidirectional scan based fault localization approach in FPGA fabric aware cellular automata topologies A Palchaudhuri, AS Dhar Journal of Parallel and Distributed Computing 130, 110-125, 2019 | 12 | 2019 |
| Speed-area optimized VLSI architecture of multi-bit cellular automaton cell based random number generator on FPGA with testable logic support A Palchaudhuri, AS Dhar Journal of Parallel and Distributed Computing 151, 13-23, 2021 | 11 | 2021 |
| Efficient Automated Implementation of Testable Cellular Automata Based Pseudorandom Generator Circuits on FPGAs. A Palchaudhuri, AA Amresh, AS Dhar Journal of Cellular Automata 12, 2017 | 11 | 2017 |
| Highly compact automated implementation of linear CA on FPGAs A Palchaudhuri, RS Chakraborty, M Salman, S Kardas, D Mukhopadhyay Cellular Automata: 11th International Conference on Cellular Automata for …, 2014 | 9 | 2014 |
| High speed FPGA fabric aware CSD recoding with run-time support for fault localization A Palchaudhuri, AS Dhar 2018 31st International Conference on VLSI Design and 2018 17th …, 2018 | 8 | 2018 |
| Redundant arithmetic based high speed carry free hybrid adders with built-in scan chain on FPGAs A Palchaudhuri, AS Dhar 2017 IEEE 24th International Conference on High Performance Computing (HiPC …, 2017 | 7 | 2017 |
| Fault localization and testability approaches for FPGA fabric aware canonic signed digit recoding implementations A Palchaudhuri, AS Dhar Journal of electronic Testing 35 (6), 779-796, 2019 | 4 | 2019 |
| Redundant Binary to Two's Complement Converter on FPGAs Through Fabric Aware Scan Based Encoding Approach for Fault Localization Support A Palchaudhuri, AS Dhar 2018 IEEE International Parallel and Distributed Processing Symposium …, 2018 | 4 | 2018 |
| Fast carry chain based architectures for two’s complement to CSD recoding on FPGAs A Palchaudhuri, AS Dhar International Symposium on Applied Reconfigurable Computing, 537-550, 2018 | 4 | 2018 |
| Architecture and design automation of high performance large adders and counters on fpga through constrained placement RS Chakraborty, A Palchaudhuri US Patent App. 15/118,120, 2017 | 4 | 2017 |
| High performance bit-sliced pipelined comparator tree for FPGAs A Palchaudhuri, AS Dhar 2016 20th International Symposium on VLSI Design and Test (VDAT), 1-6, 2016 | 4 | 2016 |
| FPGA fabric conscious architecture design and automation of speed-area efficient Margolus neighborhood based cellular automata with variegated scan path insertion A Palchaudhuri, D Anand, AS Dhar Journal of Parallel and Distributed Computing 167, 50-63, 2022 | 3 | 2022 |
| Testable architecture design for programmable cellular automata on FPGA using run-time dynamically reconfigurable look-up tables A Palchaudhuri, AS Dhar Journal of Electronic Testing 36 (4), 519-536, 2020 | 3 | 2020 |
| Primitive instantiation for speed-area efficient architecture design of cellular automata based mageto logic on FPGA with built-in testability A Palchaudhuri, AS Dhar 2020 IEEE 28th Annual International Symposium on Field-Programmable Custom …, 2020 | 3 | 2020 |
| Design Automation for Tree-based Nearest Neighborhood–aware Placement of High-speed Cellular Automata on FPGA with Scan Path Insertion A Palchaudhuri, S Sharma, AS Dhar ACM Transactions on Design Automation of Electronic Systems (TODAES) 26 (4 …, 2021 | 2 | 2021 |
| Placement aware design and automation of high speed architectures for tree-structured linear cellular automata on FPGAs with scan path insertion A Palchaudhuri, S Sharma, AS Dhar Proceedings of the 2020 ACM/SIGDA International Symposium on Field …, 2020 | 2 | 2020 |
Anindya Sundar DharProfessor, Dept. of Electronics and Electrical Communication Engineering, Indian Institute ofCorreu electrònic verificat a ece.iitkgp.ernet.in