Segueix
Valeriu Beiu
Títol
Citada per
Citada per
Any
VLSI implementations of threshold logic-a comprehensive survey
V Beiu, JM Quintana, MJ Avedillo
IEEE Transactions on Neural Networks 14 (5), 1217-1243, 2003
3102003
Majority multiplexing-economical redundant fault-tolerant designs for nanoarchitectures
S Roy, V Beiu
IEEE Transactions on Nanotechnology 4 (4), 441-451, 2005
1572005
On the reliability of majority gates full adders
W Ibrahim, V Beiu, MH Sulieman
IEEE Transactions on nanotechnology 7 (1), 56-67, 2008
872008
On single-electron technology full adders
MH Sulieman, V Beiu
IEEE transactions on nanotechnology 4 (6), 669-680, 2005
642005
Using Bayesian networks to accurately calculate the reliability of complementary metal oxide semiconductor gates
W Ibrahim, V Beiu
IEEE Transactions on Reliability 60 (3), 538-549, 2011
562011
Adder and multiplier circuits employing logic gates having discrete, weighted inputs and methods of performing combinatorial operations therewith
V Beiu
US Patent App. 09/758,080, 2001
502001
On the circuit complexity of sigmoid feedforward neural networks
V Beiu, JG Taylor
Neural Networks 9 (7), 1155-1171, 1996
481996
On nanoelectronic architectural challenges and solutions
V Beiu, U Ruckert, S Roy, J Nyathi
4th IEEE Conference on Nanotechnology, 2004., 628-631, 2004
462004
Multiplexing schemes for cost-effective fault-tolerance
S Roy, V Beiu
4th IEEE Conference on Nanotechnology, 2004., 589-592, 2004
462004
Digital integrated circuit implementations
V Beiu
Handbook of neural computation, E1. 4: 1-E1. 4: 34, 2020
442020
A novel highly reliable low-power nano architecture when von Neumann augments Kolmogorov
V Beiu
Proceedings. 15th IEEE International Conference on Application-Specific …, 2004
422004
On the exact reliability enhancements of small hammock networks
SR Cowell, V Beiu, L Dăuş, P Poulin
IEEE Access 6, 25411-25426, 2018
392018
Characterization of a 16-bit threshold logic single-electron technology adder
M Sulieman, V Beiu
2004 IEEE International Symposium on Circuits and Systems (IEEE Cat. No …, 2004
352004
On the circuit and VLSI complexity of threshold gate COMPARISON
V Beiu
Neurocomputing 19 (1-3), 77-98, 1998
351998
Area-time performances of some neural computations
V Beiu, JA Peperstraete, J Vandewalle, R Lauwereins
Proc. SPRANN 94, 664-668, 1994
341994
Lower and Upper Reliability Bounds for Consecutive--Out-of-: Systems
L Dăuş, V Beiu
IEEE Transactions on Reliability 64 (3), 1128-1135, 2015
332015
Design and analysis of SET circuits: Using MATLAB modules and SIMON
M Sulieman, V Beiu
4th IEEE Conference on Nanotechnology, 2004., 618-621, 2004
332004
GREDA: A fast and more accurate gate reliability EDA tool
W Ibrahim, V Beiu, A Beg
IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2012
322012
Efficient implementation of a neural multiplier
V Beiu, J Peperstraete, J Vandewalle, R Lauwereins
Proc. of the 2nd Int. Conf. on Microelectronics for Neural Networks, 217-230, 1991
321991
Entropy bounds for classification algorithms
V Beiu
Neural Network World 6 (4), 497-505, 1996
311996
En aquests moments el sistema no pot dur a terme l'operació. Torneu-ho a provar més tard.
Articles 1–20