Anindya Sundar Dhar

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Ayan PalchaudhuriIndian Institute of Technology BhubaneswarCorreu electrònic verificat a iitbbs.ac.in
Atin MukherjeeAssistant Professor, National Institute of Technology RourkelaCorreu electrònic verificat a nitrkl.ac.in
Indrajit ChakrabartiProfessor, Dept. of Electronics and Electrical Communication Engineering, IIT KharagpurCorreu electrònic verificat a ece.iitkgp.ernet.in
Ashis Kumar MalProfessor of ECE, NIT DurgapurCorreu electrònic verificat a ece.nitdgp.ac.in
Subrahmanyam MulaAssistant Professor at IIT PalakkadCorreu electrònic verificat a iitpkd.ac.in
V C GogineniUniversity of Southern DenmarkCorreu electrònic verificat a mmmi.sdu.dk
Mamata PanigrahyAsst. ProfessorCorreu electrònic verificat a kiit.ac.in
Koushik MaharatnaProfessor, School of Electronics and Computer Science, University of SouthamptonCorreu electrònic verificat a ecs.soton.ac.uk
avishek sinha royLogic Design Engineer at IBM (ISDL)Correu electrònic verificat a ibm.com
Dr Lakshmi Boppana, PhD(IIT, Kharag...Professor, National institute of Technology, WarangalCorreu electrònic verificat a nitw.ac.in
Arindam BasuProfessor, City University of Hong Kong (past Associate Professor of EEE at NTU)Correu electrònic verificat a cityu.edu.hk
Mrityunjoy Chakraborty (Latest)Professor, E & ECE, IIT, KharagpurCorreu electrònic verificat a ece.iitkgp.ernet.in
TANMAI KULSHRESHTHADayalbagh Educational Institute AgraCorreu electrònic verificat a dei.ac.in
Dr. Achintya HalderTexas Instruments Inc; Ex-Assistant Professor at IIT KharagpurCorreu electrònic verificat a ece.iitkgp.ernet.in
Rajarshi MahapatraProfessor, IIIT Naya RaipurCorreu electrònic verificat a ieee.org
Debasish DattaProfessor (Retired), IIT Kharagpur, IndiaCorreu electrònic verificat a ece.iitkgp.ac.in
Rohan MukherjeeAssociate Professor, International Management Institute KolkataCorreu electrònic verificat a imi-k.edu.in
Debasis SamantaProfessor, Computer Science & Engineering, Indian Institute of Technology KharagpurCorreu electrònic verificat a iitkgp.ac.in
Monalisa SarmaAssistant Professor of Reliability EngineeringCorreu electrònic verificat a iitkgp.ac.in
Rakesh BiswasIndian Institute of Information Technology GuwahatiCorreu electrònic verificat a iiitg.ac.in

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Anindya Sundar Dhar

Professor, Dept. of Electronics and Electrical Communication Engineering, Indian Institute of

Correu electrònic verificat a ece.iitkgp.ernet.in

VLSI Architecture Design


Títol Ordena per cites Ordena per any Ordena per títol	Citada per Citada per	Any
CORDIC architectures: A survey B Lakshmi, AS Dhar VLSI design 2010 (1), 794891, 2010	130	2010
FPGA realization of a CORDIC based FFT processor for biomedical signal processing A Banerjee, AS Dhar, S Banerjee Microprocessors and Microsystems 25 (3), 131-142, 2001	93	2001
A VLSI array architecture for realization of DFT, DHT, DCT and DST K Maharatna, AS Dhar, S Banerjee Signal Processing 81 (9), 1813-1822, 2001	73	2001
An array architecture for fast computation of discrete Hartley transform AS Dhar, S Banerjee IEEE transactions on circuits and systems 38 (9), 1095-1098, 1991	71	1991
CORDIC-based unified VLSI architecture for implementing window functions for real time spectral analysis KC Ray, AS Dhar IEE Proceedings-Circuits, Devices and Systems 153 (6), 539-544, 2006	41	2006
Real-time fault-tolerance with hot-standby topology for conditional sum adder A Mukherjee, AS Dhar Microelectronics Reliability 55 (3-4), 704-712, 2015	38	2015
Architectural design and FPGA implementation of radix-4 CORDIC processor K Bhattacharyya, R Biswas, AS Dhar, S Banerjee Microprocessors and Microsystems 34 (2-4), 96-101, 2010	33	2010
A trigonometric formulation of the LMS algorithm for realization on pipelined CORDIC M Chakraborty, AS Dhar, MH Lee IEEE Transactions on Circuits and Systems II: Express Briefs 52 (9), 530-534, 2005	29	2005
Algorithm and VLSI architecture design of proportionate-type LMS adaptive filters for sparse system identification S Mula, VC Gogineni, AS Dhar IEEE Transactions on Very Large Scale Integration (VLSI) Systems 26 (9 …, 2018	28	2018
Algorithm and architecture design of adaptive filters with error nonlinearities S Mula, VC Gogineni, AS Dhar IEEE Transactions on Very Large Scale Integration (VLSI) Systems 25 (9 …, 2017	27	2017
VLSI architecture for parallel radix-4 CORDIC B Lakshmi, AS Dhar Microprocessors and Microsystems 37 (1), 79-86, 2013	25	2013
VLSI architecture for low latency radix-4 CORDIC B Lakshmi, AS Dhar Computers & Electrical Engineering 37 (6), 1032-1042, 2011	23	2011
Low-delay parallel architecture for fractal image compression M Panigrahy, I Chakrabarti, AS Dhar Circuits, Systems, and Signal Processing 35, 897-917, 2016	21	2016
CORDIC unit K Maharatna, E Grass, B Swapna, DA Sundar US Patent 7,606,852, 2009	21	2009
FPGA implementation of discrete fractional Fourier transform M Prasad, KC Ray, AS Dhar 2010 International Conference on Signal Processing and Communications (SPCOM …, 2010	20	2010
Efficient implementation of scan register insertion on integer arithmetic cores for FPGAs A Palchaudhuri, AS Dhar 2016 29th International Conference on VLSI Design and 2016 15th …, 2016	18	2016
Built-in fault localization circuitry for high performance FPGA based implementations A Palchaudhuri, AS Dhar Journal of Electronic Testing 33, 529-537, 2017	15	2017
A variable RF carrier modulation scheme for ultralow power wireless body-area network A Ghosh, A Halder, AS Dhar IEEE Systems Journal 6 (2), 305-316, 2011	15	2011
Robust proportionate adaptive filter architectures under impulsive noise S Mula, VC Gogineni, AS Dhar IEEE Transactions on Very Large Scale Integration (VLSI) Systems 27 (5 …, 2019	14	2019
A novel approach for fast and accurate mean error distance computation in approximate adders AS Roy, AS Dhar 2018 IEEE International Symposium on Circuits and Systems (ISCAS), 1-5, 2018	14	2018

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