| Fabrication and Analysis of a Heterojunction Line Tunnel FET AM Walke, A Vandooren, R Rooyackers, D Leonelli, A Hikavyy, R Loo, ... IEEE Transactions on Electron Devices 61 (3), 707-715, 2014 | 151 | 2014 |
| Part I: Impact of field-induced quantum confinement on the subthreshold swing behavior of line TFETs AM Walke, AS Verhulst, A Vandooren, D Verreck, E Simoen, VR Rao, ... IEEE transactions on electron devices 60 (12), 4057-4064, 2013 | 64 | 2013 |
| A new complementary hetero-junction vertical tunnel-FET integration scheme R Rooyackers, A Vandooren, AS Verhulst, A Walke, K Devriendt, ... 2013 IEEE International Electron Devices Meeting, 4.2. 1-4.2. 4, 2013 | 62 | 2013 |
| The impact of sequential-3D integration on semiconductor scaling roadmap A Mallik, A Vandooren, L Witters, A Walke, J Franco, Y Sherazi, P Weckx, ... 2017 IEEE International Electron Devices Meeting (IEDM), 32.1. 1-31.1. 4, 2017 | 60 | 2017 |
| Ge-source vertical tunnel FETs using a novel replacement-source integration scheme R Rooyackers, A Vandooren, AS Verhulst, AM Walke, E Simoen, ... IEEE transactions on electron devices 61 (12), 4032-4039, 2014 | 46 | 2014 |
| First Demonstration of 3D stacked Finfets at a 45nm fin pitch and 110nm gate pitch technology on 300mm wafers A Vandooren, J Franco, Z Wu, B Parvais, W Li, L Witters, A Walke, L Peng, ... 2018 IEEE International Electron Devices Meeting (IEDM), 7.1. 1-7.1. 4, 2018 | 40 | 2018 |
| High-endurance ferroelectric (La, Y) and (La, Gd) Co-doped hafnium zirconate grown by atomic layer deposition MI Popovici, AM Walke, J Bizindavyi, J Meersschaut, K Banerjee, ... ACS Applied Electronic Materials 4 (4), 1823-1831, 2022 | 38 | 2022 |
| Electrical investigation of wake-up in high endurance fatigue-free La and Y doped HZO metal–ferroelectric–metal capacitors AM Walke, MI Popovici, K Banerjee, S Clima, P Kumbhare, J Desmet, ... IEEE Transactions on Electron Devices 69 (8), 4744-4749, 2022 | 33 | 2022 |
| Investigation of the Subthreshold Swing in Vertical Tunnel-FETs Using and Anneals A Vandooren, AM Walke, AS Verhulst, R Rooyackers, N Collaert, ... IEEE Transactions on Electron Devices 61 (2), 359-364, 2014 | 29 | 2014 |
| 3D sequential stacked planar devices on 300 mm wafers featuring replacement metal gate junction-less top devices processed at 525° C with improved reliability A Vandooren, J Franco, B Parvais, Z Wu, L Witters, A Walke, W Li, L Peng, ... 2018 IEEE Symposium on VLSI Technology, 69-70, 2018 | 28 | 2018 |
| First demonstration of III-V HBTs on 300 mm Si substrates using nano-ridge engineering A Vais, L Witters, Y Mols, AS Hernandez, A Walke, H Yu, M Baryshnikova, ... 2019 IEEE International Electron Devices Meeting (IEDM), 9.1. 1-9.1. 4, 2019 | 27 | 2019 |
| Part II: Investigation of subthreshold swing in line tunnel FETs using bias stress measurements AM Walke, A Vandooren, B Kaczer, AS Verhulst, R Rooyackers, E Simoen, ... IEEE transactions on Electron Devices 60 (12), 4065-4072, 2013 | 25 | 2013 |
| High performance La-doped HZO based ferroelectric capacitors by interfacial engineering MI Popovici, J Bizindavyi, P Favia, S Clima, MNK Alam, ... 2022 International Electron Devices Meeting (IEDM), 6.4. 1-6.4. 4, 2022 | 22 | 2022 |
| Ferroelectric La‐Doped ZrO2/HfxZr1−xO2 Bilayer Stacks with Enhanced Endurance M Popovici, AM Walke, K Banerjee, N Ronchi, J Meersschaut, U Celano, ... physica status solidi (RRL)–Rapid Research Letters 15 (5), 2100033, 2021 | 22 | 2021 |
| Impact of Charge Trapping and Depolarization on Data Retention Using Simultaneous P–V and I–V in HfO₂-Based Ferroelectric FET Y Higashi, N Ronchi, B Kaczer, MNK Alam, BJ O’Sullivan, K Banerjee, ... IEEE Transactions on Electron Devices 68 (9), 4391-4396, 2021 | 20 | 2021 |
| 3-D sequential stacked planar devices featuring low-temperature replacement metal gate junctionless top devices with improved reliability A Vandooren, J Franco, B Parvais, Z Wu, L Witters, A Walke, W Li, L Peng, ... IEEE Transactions on Electron Devices 65 (11), 5165-5171, 2018 | 20 | 2018 |
| Multi-threshold voltage field effect transistor and manufacturing method thereof AM Walke, CH Hsieh, CM Chu, YH Kuo US Patent 9,837,416, 2017 | 20 | 2017 |
| Sequential 3D: Key integration challenges and opportunities for advanced semiconductor scaling A Vandooren, L Witters, J Franco, A Mallik, B Parvais, Z Wu, A Walke, ... 2018 International Conference on IC Design & Technology (ICICDT), 145-148, 2018 | 18 | 2018 |
| Improved MW of IGZO-channel FeFET by reading scheme optimization and interfacial engineering Z Chen, N Ronchi, A Walke, K Banerjee, MI Popovici, K Katcko, ... 2023 IEEE International Memory Workshop (IMW), 1-4, 2023 | 15 | 2023 |
| Engineering strain and texture in ferroelectric scandium-doped aluminium nitride SRC McMitchell, AM Walke, K Banerjee, S Mertens, X Piao, M Mao, ... ACS Applied Electronic Materials 5 (2), 858-864, 2023 | 15 | 2023 |