| A 112 Gb/s –8.2 dBm Sensitivity 4-PAM Linear TIA in 16nm CMOS with Co-Packaged Photodiodes D Patel, A Sharif-Bakhtiar, T Chan Carusone 2022 IEEE Custom Integrated Circuits Conference (CICC), 2022 | 39 | 2022 |
| Hybrid latch-type offset tolerant sense amplifier for low-voltage SRAMs D Patel, A Neale, D Wright, M Sachdev IEEE Transactions on Circuits and Systems I: Regular Papers 66 (7), 2519-2532, 2019 | 21 | 2019 |
| Body biased sense amplifier with auto-offset mitigation for low-voltage SRAMs D Patel, A Neale, D Wright, M Sachdev IEEE Transactions on Circuits and Systems I: Regular Papers 68 (8), 3265-3278, 2021 | 19 | 2021 |
| 0.23-V sample-boost-latch-based offset tolerant sense amplifier D Patel, M Sachdev IEEE Solid-State Circuits Letters 1 (1), 6-9, 2018 | 18 | 2018 |
| Co-Packaged 100+ Gbps Optical Communication Receiver Front-Ends in FinFET CMOS DR Patel University of Toronto (Canada), 2020 | 3 | 2020 |
| Experimental study of the equalization requirements of a 2.5 D co-packaged 16-nm cmos optical receiver up to 160 gb/s D Patel, B Radi, A Sharif-Bakhtiar, AC Carusone European Conference and Exhibition on Optical Communication, Tu5. 26, 2022 | 1 | 2022 |
| Sense amplifier offset characterisation and test implications for low-voltage SRAMs in 65 nm D Patel, D Wright, M Sachdev 2018 IEEE 23rd European Test Symposium (ETS), 1-6, 2018 | 1 | 2018 |
| Optimizing the Photodetector/Analog Front-End Interface in Optical Communication Receivers B Radi, Z Li, D Patel, AC Carusone IEEE Transactions on Signal and Power Integrity 2, 111-121, 2023 | | 2023 |
| A 112-Gb/s –8.2-dBm Sensitivity 4-PAM Linear TIA in 16-nm CMOS With Co-Packaged Photodiodes D Patel, A Sharif-Bakhtiar, T Chan Carusone IEEE Journal of Solid-State Circuits (JSSC) 58 (3), 771-784, 2022 | | 2022 |
Manoj SachdevProfessor of Electrical and Computer Engineering, University of WaterlooE-mailová adresa ověřena na: uwaterloo.ca
