| Low-power programmable PRPG with test compression capabilities M Filipek, G Mrugalski, N Mukherjee, B Nadeau-Dostie, J Rajski, J Solecki, ... IEEE Transactions on Very Large Scale Integration (VLSI) Systems 23 (6 …, 2014 | 49 | 2014 |
| Trimodal scan-based test paradigm G Mrugalski, J Rajski, J Solecki, J Tyszer, C Wang IEEE Transactions on Very Large Scale Integration (VLSI) Systems 25 (3 …, 2016 | 41 | 2016 |
| Logic BIST with capture-per-clock hybrid test points E Moghaddam, N Mukherjee, J Rajski, J Solecki, J Tyszer, J Zawada IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2018 | 34 | 2018 |
| Full-scan LBIST with capture-per-cycle hybrid test points S Milewski, N Mukherjee, J Rajski, J Solecki, J Tyszer, J Zawada 2017 IEEE International Test Conference (ITC), 1-9, 2017 | 19 | 2017 |
| Test time and area optimized BrST scheme for automotive ICs N Mukherjee, D Tille, M Sapati, Y Liu, J Mayer, S Milewski, E Moghaddam, ... 2019 IEEE International Test Conference (ITC), 1-10, 2019 | 17 | 2019 |
| Staggered ATPG with capture-per-cycle observation test points Y Liu, J Rajski, SM Reddy, J Solecki, J Tyszer 2018 IEEE 36th VLSI Test Symposium (VTS), 1-6, 2018 | 17 | 2018 |
| Deterministic Built-In Self-Test G Mrugalski, J Rajski, L Rybak, J Solecki, J Tyszer US Patent App. 15/051,063, 2016 | 16* | 2016 |
| Time and area optimized testing of automotive ICs N Mukherjee, D Tille, M Sapati, Y Liu, J Mayer, S Milewski, E Moghaddam, ... IEEE Transactions on Very Large Scale Integration (VLSI) Systems 29 (1), 76-88, 2020 | 14 | 2020 |
| Star-EDT: Deterministic On-Chip Scheme Using Compressed Test Patterns G Mrugalski, J Rajski, Ł Rybak, J Solecki, J Tyszer IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2017 | 13 | 2017 |
| Low power programmable PRPG with enhanced fault coverage gradient J Solecki, J Tyszer, G Mrugalski, N Mukherjee, J Rajski 2012 IEEE International Test Conference, 1-9, 2012 | 13 | 2012 |
| Test-per-clock based on dynamically-partitioned reconfigurable scan chains J Rajski, J Solecki, J Tyszer, G Mrugalski US Patent App. 15/150,147, 2016 | 12 | 2016 |
| TestExpress-new time-effective scan-based deterministic test paradigm G Mrugalski, J Rajski, J Solecki, J Tyszer, C Wang 2015 IEEE 24th Asian Test Symposium (ATS), 19-24, 2015 | 11 | 2015 |
| Test-Per-Clock Based On Dynamically-Partitioned Reconfigurable Scan Chains J Rajski, J Solecki, J Tyszer, G Mrugalski US Patent App. 13/919,974, 2014 | 10 | 2014 |
| Fault diagnosis with orthogonal compactors in scan-based designs B Benware, G Mrugalski, A Pogiel, J Rajski, J Solecki, J Tyszer Journal of Electronic Testing 27, 599-609, 2011 | 9 | 2011 |
| Fault-driven scan chain configuration for test-per-clock J Rajski, J Solecki, J Tyszer, G Mrugalski US Patent App. 13/919,998, 2014 | 7 | 2014 |
| Test application time reduction using capture-per-cycle test points J Rajski, S Milewski, N Mukherjee, J Solecki, J Tyszer, J Zawada US Patent 10,509,072, 2019 | 6 | 2019 |
| Diagnosis of failing scan cells through orthogonal response compaction B Benware, G Mrugalski, A Pogiel, J Rajski, J Solecki, J Tyszer 2010 15th IEEE European Test Symposium, 221-226, 2010 | 6 | 2010 |
| Scan chain configuration for test-per-clock based on circuit topology J Rajski, J Solecki, J Tyszer, G Mrugalski US Patent 9,009,553, 2015 | 5 | 2015 |
| Scan chain stitching for test-per-clock J Rajski, J Solecki, J Tyszer, G Mrugalski US Patent 10,379,161, 2019 | 4 | 2019 |
| Test generation for test-per-clock J Rajski, J Solecki, J Tyszer, G Mrugalski US Patent 9,347,993, 2016 | 4 | 2016 |
