David Z. Pan

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Bei YuThe Chinese University of Hong KongVerificeret mail på cse.cuhk.edu.hk
Jiaqi GuAssistant Professor, School of ECEE, Arizona State UniversityVerificeret mail på asu.edu
Yibo LinAssistant Professor at Peking UniversityVerificeret mail på pku.edu.cn
chen, ray t.Keys and Joan Curry/Cullen Trust Endowed Chair Professor, UT Austin; MURI Center Director, FounderVerificeret mail på ece.utexas.edu
Zheng ZhaoUniversity of Texas at AustinVerificeret mail på utexas.edu
Chenghao FengSenior photonics engineer, Ph.D., University of Texas at AustinVerificeret mail på utexas.edu
Meng LiPeking University; Ex-FacebookVerificeret mail på pku.edu.cn
Nan Sun (孙楠)Professor, Tsinghua University, IEEE FellowVerificeret mail på tsinghua.edu.cn
Mingjie LiuNVIDIA CorporationVerificeret mail på nvidia.com
Zhoufeng YingPhD, the university of Texas at AustinVerificeret mail på utexas.edu
Minsik ChoAI/ML at AppleVerificeret mail på apple.com
Keren ZhuFudan UniversityVerificeret mail på fudan.edu.cn
Xiyuan TangPeking UniversityVerificeret mail på pku.edu.cn
Xiaoqing XuGoogle DeepMindVerificeret mail på google.com
Duo DingEngineerVerificeret mail på utexas.edu
Jhih-Rong GaoUniversity of Texas at AustinVerificeret mail på utexas.edu
Shounak DharIntel Corporation; University of Texas at AustinVerificeret mail på utexas.edu
Hanqing ZhuUniversity of Texas at AustinVerificeret mail på utexas.edu
Jingsheng Jason CongVolgenau Chair for Engineering Excellence, Computer Science and Electrical Engineering, UniversityVerificeret mail på cs.ucla.edu
Yier JinAssociate Professor, University of FloridaVerificeret mail på ece.ufl.edu

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David Z. Pan

Professor, Silicon Labs Endowed Chair, ECE Dept., University of Texas at Austin

Verificeret mail på ece.utexas.edu - Startside

Electronic Design Automation Design for Manufacturing VLSI Hardware Machine Learning


Titel Sortér efter henvisninger Sortér efter årstal Sortér efter titel	Citeret af Citeret af	År
AppSAT: Approximately deobfuscating integrated circuits K Shamsi, M Li, T Meade, Z Zhao, DZ Pan, Y Jin 2017 IEEE International Symposium on Hardware Oriented Security and Trust …, 2017	377	2017
CELONCEL: Effective design technique for 3-D monolithic integration targeting high performance integrated circuits S Bobba, A Chakraborty, O Thomas, P Batude, T Ernst, O Faynot, DZ Pan, ... 16th Asia and South Pacific Design Automation Conference (ASP-DAC 2011), 336-343, 2011	321	2011
Dreamplace: Deep learning toolkit-enabled gpu acceleration for modern vlsi placement Y Lin, S Dhar, W Li, H Ren, B Khailany, DZ Pan Proceedings of the 56th Annual Design Automation Conference 2019, 1-6, 2019	280	2019
Multi-scale high-resolution vision transformer for semantic segmentation J Gu, H Kwon, D Wang, W Ye, M Li, YH Chen, L Lai, V Chandra, DZ Pan Proceedings of the IEEE/CVF conference on computer vision and pattern …, 2022	257	2022
Interconnect design for deep submicron ICs Z Pan, L He, CK Koh, KY Khoo 1997 Proceedings of IEEE International Conference on Computer Aided Design …, 1997	253	1997
An energy-efficient comparator with dynamic floating inverter amplifier X Tang, L Shen, B Kasap, X Yang, W Shi, A Mukherjee, DZ Pan, N Sun IEEE Journal of Solid-State Circuits 55 (4), 1011-1022, 2020	229	2020
Pushing ASIC performance in a power envelope R Puri, L Stok, J Cohn, D Kung, D Pan, D Sylvester, A Srivastava, ... Proceedings of the 40th annual Design Automation Conference, 788-793, 2003	218	2003
Provably secure camouflaging strategy for IC protection M Li, K Shamsi, T Meade, Z Zhao, B Yu, Y Jin, DZ Pan IEEE transactions on computer-aided design of integrated circuits and …, 2017	205	2017
Cyclic obfuscation for creating SAT-unresolvable circuits K Shamsi, M Li, T Meade, Z Zhao, DZ Pan, Y Jin Proceedings of the Great Lakes Symposium on VLSI 2017, 173-178, 2017	198	2017
Improved crosstalk modeling for noise constrained interconnect optimization J Cong, DZ Pan, PV Srinivas Proceedings of the 2001 Asia and South Pacific Design Automation Conference …, 2001	196	2001
Buffer block planning for interconnect-driven floorplanning J Cong, T Kong, DZ Pan 1999 IEEE/ACM International Conference on Computer-Aided Design. Digest of …, 1999	192	1999
Redundant-via enhanced maze routing for yield improvement G Xu, LD Huang, DZ Pan, MDF Wong Proceedings of the 2005 Asia and South Pacific Design Automation Conference …, 2005	191	2005
Layout decomposition for triple patterning lithography B Yu, K Yuan, D Ding, DZ Pan IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2015	189	2015
Quantumnas: Noise-adaptive search for robust quantum circuits H Wang, Y Ding, J Gu, Y Lin, DZ Pan, FT Chong, S Han 2022 IEEE International Symposium on High-Performance Computer Architecture …, 2022	184	2022
BoxRouter: A new global router based on box expansion and progressive ILP M Cho, DZ Pan Proceedings of the 43rd annual Design Automation Conference, 373-378, 2006	174	2006
A high-performance droplet routing algorithm for digital microfluidic biochips M Cho, DZ Pan IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2008	167	2008
Double patterning layout decomposition for simultaneous conflict and stitch minimization K Yuan, JS Yang, D Pan Proceedings of the 2009 international symposium on Physical design, 107-114, 2009	158	2009
TSV stress-aware full-chip mechanical reliability analysis and optimization for 3D IC M Jung, J Mitra, DZ Pan, SK Lim Proceedings of the 48th Design Automation Conference, 188-193, 2011	156	2011
TSV stress aware timing analysis with applications to 3D-IC layout optimization J Yang, K Athikulwongse, YJ Lee, SK Lim, DZ Pan Proceedings of the 47th Design Automation Conference, 803-806, 2010	152	2010
BoxRouter 2.0: Architecture and implementation of a hybrid and robust global router M Cho, K Lu, K Yuan, DZ Pan 2007 IEEE/ACM International Conference on Computer-Aided Design, 503-508, 2007	148	2007

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