| Capacitor-less, long-retention (> 400s) DRAM cell paving the way towards low-power and high-density monolithic 3D DRAM A Belmonte, H Oh, N Rassoul, GL Donadio, J Mitard, H Dekkers, ... 2020 IEEE International Electron Devices Meeting (IEDM), 28.2. 1-28.2. 4, 2020 | 132 | 2020 |
| InGaAs Gate-All-Around Nanowire Devices on 300mm Si Substrates N Waldron, C Merckling, L Teugels, P Ong, SAU Ibrahim, F Sebaai, ... IEEE Electron Device Letters 35 (11), 1097-1099, 2014 | 121 | 2014 |
| An InGaAs/InP quantum well FinFet using the replacement fin process integrated in an RMG flow on 300 mm Si substrates N Waldron, C Merckling, W Guo, P Ong, L Teugels, S AnsarI, ... Symp. VLSI Technol. Dig. Tech. Papers (VLSIT), 32-33, 2014 | 110 | 2014 |
| High-aspect-ratio ruthenium lines for buried power rail A Gupta, S Kundu, L Teugels, J Bommels, C Adelmann, N Heylen, ... 2018 IEEE International Interconnect Technology Conference (IITC), 4-6, 2018 | 63 | 2018 |
| Gate-all-around InGaAs nanowire FETS with peak transconductance of 2200μS/μm at 50nm Lg using a replacement Fin RMG flow N Waldron, S Sioncke, J Franco, L Nyns, A Vais, X Zhou, HC Lin, ... 2015 IEEE International Electron Devices Meeting (IEDM), 31.1. 1-31.1. 4, 2015 | 62 | 2015 |
| Investigation of percarbonate based slurry chemistry for controlling galvanic corrosion during CMP of ruthenium MC Turk, SE Rock, HP Amanapu, LG Teugels, D Roy ECS Journal of Solid State Science and Technology 2 (5), P205, 2013 | 60 | 2013 |
| Tailoring IGZO-TFT architecture for capacitorless DRAM, demonstrating > 103s retention, >1011 cycles endurance and Lg scalability down to 14nm A Belmonte, H Oh, S Subhechha, N Rassoul, H Hody, H Dekkers, ... 2021 IEEE International Electron Devices Meeting (IEDM), 10.6. 1-10.6. 4, 2021 | 58 | 2021 |
| Role of guanidine carbonate and crystal orientation on chemical mechanical polishing of ruthenium films HP Amanapu, KV Sagi, LG Teugels, SV Babu ECS Journal of Solid State Science and Technology 2 (11), P445, 2013 | 55 | 2013 |
| First demonstration of sub-12 nm Lg gate last IGZO-TFTs with oxygen tunnel architecture for front gate devices S Subhechha, N Rassoul, A Belmonte, R Delhougne, K Banerjee, ... 2021 Symposium on VLSI Technology, 1-2, 2021 | 52 | 2021 |
| Chemical mechanical polishing of chemical vapor deposited Co films with minimal corrosion in the Cu/Co/Mn/SiCOH patterned structures KV Sagi, LG Teugels, MH Van Der Veen, H Struyf, SR Alety, SV Babu ECS Journal of Solid State Science and Technology 6 (5), P276, 2017 | 52 | 2017 |
| Chiral domains achieved by surface adsorption of achiral nickel tetraphenyl-or octaethylporphyrin on smooth and locally kinked Au (111) LG Teugels, LG Avila-Bront, SJ Sibener The Journal of Physical Chemistry C 115 (6), 2826-2834, 2011 | 41 | 2011 |
| Buried power rail integration with FinFETs for ultimate CMOS scaling A Gupta, OV Pedreira, G Arutchelvan, H Zahedmanesh, K Devriendt, ... IEEE Transactions on Electron Devices 67 (12), 5349-5354, 2020 | 40 | 2020 |
| First Demonstration of 3D stacked Finfets at a 45nm fin pitch and 110nm gate pitch technology on 300mm wafers A Vandooren, J Franco, Z Wu, B Parvais, W Li, L Witters, A Walke, L Peng, ... 2018 IEEE International Electron Devices Meeting (IEDM), 7.1. 1-7.1. 4, 2018 | 39 | 2018 |
| 28nm pitch single exposure patterning readiness by metal oxide resist on 0.33 NA EUV lithography D De Simone, L Kljucar, P Das, R Blanc, C Beral, J Severi, ... Extreme Ultraviolet (EUV) Lithography XII 11609, 43-53, 2021 | 37 | 2021 |
| Electrical characterization of CNT contacts with Cu Damascene top contact MH Van Der Veen, B Vereecke, C Huyghebaert, DJ Cott, M Sugiura, ... Microelectronic engineering 106, 106-111, 2013 | 36 | 2013 |
| Vertical nanowire and nanosheet FETs: device features, novel schemes for improved process control and enhanced mobility, potential for faster & more energy efficient circuits A Veloso, G Eneman, T Huynh-Bao, A Chasin, E Simoen, E Vecchio, ... 2019 IEEE International Electron Devices Meeting (IEDM), 11.1. 1-11.1. 4, 2019 | 32 | 2019 |
| Replacement fin processing for III–V on Si: From FinFets to nanowires N Waldron, C Merckling, L Teugels, P Ong, F Sebaai, K Barla, N Collaert, ... Solid-State Electronics 115, 81-91, 2016 | 31 | 2016 |
| Inflection points in interconnect research and trends for 2nm and beyond in order to solve the RC bottleneck Z Tőkei, V Vega, G Murdoch, M O’Toole, K Croes, R Baert, ... 2020 IEEE International Electron Devices Meeting (IEDM), 32.2. 1-32.2. 4, 2020 | 29 | 2020 |
| 3D sequential stacked planar devices on 300 mm wafers featuring replacement metal gate junction-less top devices processed at 525° C with improved reliability A Vandooren, J Franco, B Parvais, Z Wu, L Witters, A Walke, W Li, L Peng, ... 2018 IEEE Symposium on VLSI Technology, 69-70, 2018 | 28 | 2018 |
| Ultra-low Leakage IGZO-TFTs with Raised Source/Drain for Vt > 0 V and Ion > 30 µA/µm S Subhechha, N Rassoul, A Belmonte, H Hody, H Dekkers, MJ van Setten, ... 2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and …, 2022 | 24 | 2022 |
