| Dielectric breakdown mechanisms in gate oxides S Lombardo, JH Stathis, BP Linder, KL Pey, F Palumbo, CH Tung Journal of applied physics 98 (12), 2005 | 561 | 2005 |
| Structures and techniques for atomic layer deposition S Aoyama, RD Clark, SP Consiglio, M Hopstaken, H Jagannathan, ... US Patent 8,722,548, 2014 | 431 | 2014 |
| High performance 14nm SOI FinFET CMOS technology with 0.0174µm2 embedded DRAM and 15 levels of Cu metallization CH Lin, B Greene, S Narasimha, J Cai, A Bryant, C Radens, V Narayanan, ... 2014 IEEE International Electron Devices Meeting, 3.8. 1-3.8. 3, 2014 | 195 | 2014 |
| The impact of gate-oxide breakdown on SRAM stability R Rodriguez, JH Stathis, BP Linder, S Kowalczyk, CT Chuang, RV Joshi, ... IEEE Electron Device Letters 23 (9), 559-561, 2002 | 138 | 2002 |
| Fundamental aspects of HfO2-based high-k metal gate stack reliability and implications on tinv-scaling E Cartier, A Kerber, T Ando, MM Frank, K Choi, S Krishnan, B Linder, ... 2011 International Electron Devices Meeting, 18.4. 1-18.4. 4, 2011 | 127 | 2011 |
| Examination of flatband and threshold voltage tuning of HfO2∕ TiN field effect transistors by dielectric cap layers S Guha, VK Paruchuri, M Copel, V Narayanan, YY Wang, PE Batson, ... Applied physics letters 90 (9), 2007 | 124 | 2007 |
| High-performance high-κ/metal gates for 45nm CMOS and beyond with gate-first processing M Chudzik, B Doris, R Mo, J Sleight, E Cartier, C Dewan, D Park, H Bu, ... 2007 IEEE symposium on VLSI technology, 194-195, 2007 | 123 | 2007 |
| Voltage dependence of hard breakdown growth and the reliability implication in thin dielectrics BP Linder, S Lombardo, JH Stathis, A Vayshenker, DJ Frank IEEE Electron Device Letters 23 (11), 661-663, 2002 | 115 | 2002 |
| Metal gate CMOS with at least a single gate metal and dual gate dielectrics BB Doris, YH Kim, BP Linder, V Narayanan, VK Paruchuri US Patent 7,432,567, 2008 | 111 | 2008 |
| Band-edge high-performance high-k/metal gate n-MOSFETs using cap layers containing group IIA and IIIB elements with gate-first processing for 45 nm and beyond TC Chen, G Shahidi, S Guha, M Ieong, MP Chudzik, R Jammy, ... 2006 Symposium on VLSI Technology, 2006. Digest of Technical Papers., 178-179, 2006 | 109 | 2006 |
| 22nm High-performance SOI technology featuring dual-embedded stressors, Epi-Plate High-K deep-trench embedded DRAM and self-aligned Via 15LM BEOL S Narasimha, P Chang, C Ortolland, D Fried, E Engbrecht, K Nummy, ... 2012 International Electron Devices Meeting, 3.3. 1-3.3. 4, 2012 | 107 | 2012 |
| A model for gate-oxide breakdown in CMOS inverters R Rodriguez, JH Stathis, BP Linder IEEE Electron Device Letters 24 (2), 114-116, 2003 | 107 | 2003 |
| High performance CMOS circuits, and methods for fabricating the same J Arnold, G Biery, A Callegari, TC Chen, M Chudzik, B Doris, M Gribelyuk, ... US Patent App. 11/323,578, 2007 | 106 | 2007 |
| Role of oxygen vacancies in V/sub FB//V/sub t/stability of pFET metals on HfO/sub 2 E Cartier, FR McFeely, V Narayanan, P Jamison, BP Linder, M Copel, ... Digest of Technical Papers. 2005 Symposium on VLSI Technology, 2005., 230-231, 2005 | 104 | 2005 |
| Fundamental understanding and optimization of PBTI in nFETs with SiO2/HfO2 gate stack E Cartier, BP Linder, V Narayanan, VK Paruchuri 2006 International Electron Devices Meeting, 1-4, 2006 | 103 | 2006 |
| Gate oxide breakdown under current limited constant voltage stress BP Linder, JH Stathis, RA Wachnik, E Wu, SA Cohen, A Ray, ... 2000 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No …, 2000 | 90 | 2000 |
| Growth and scaling of oxide conduction after breakdown BP Linder, JH Stathis, DJ Frank, S Lombardo, A Vayshenker 2003 IEEE International Reliability Physics Symposium Proceedings, 2003 …, 2003 | 76 | 2003 |
| Impact of back bias on ultra-thin body and BOX (UTBB) devices Q Liu, F Monsieur, A Kumar, T Yamamoto, A Yagishita, P Kulkarni, ... 2011 Symposium on VLSI Technology-Digest of Technical Papers, 160-161, 2011 | 69 | 2011 |
| PBTI under dynamic stress: From a single defect point of view K Zhao, JH Stathis, BP Linder, E Cartier, A Kerber 2011 International Reliability Physics Symposium, 4A. 3.1-4A. 3.9, 2011 | 64 | 2011 |
| Modeling and experimental verification of the effect of gate oxide breakdown on CMOS inverters R Rodriguez, JH Stathis, BP Linder 2003 IEEE International Reliability Physics Symposium Proceedings, 2003 …, 2003 | 63 | 2003 |
