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Moinuddin Qureshi
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Scalable high performance main memory system using phase-change memory technology
MK Qureshi, V Srinivasan, JA Rivers
Proceedings of the 36th annual international symposium on Computer …, 2009
18462009
Utility-based cache partitioning: A low-overhead, high-performance, runtime mechanism to partition shared caches
MK Qureshi, YN Patt
2006 39th Annual IEEE/ACM International Symposium on Microarchitecture …, 2006
14872006
Adaptive insertion policies for high performance caching
MK Qureshi, A Jaleel, YN Patt, SC Steely, J Emer
ACM SIGARCH Computer Architecture News 35 (2), 381-391, 2007
9912007
Enhancing lifetime and security of PCM-based main memory with start-gap wear leveling
MK Qureshi, J Karidis, M Franceschini, V Srinivasan, L Lastras, B Abali
Proceedings of the 42nd annual IEEE/ACM international symposium on …, 2009
9782009
Not all qubits are created equal: A case for variability-aware policies for NISQ-era quantum computers
SS Tannu, MK Qureshi
Proceedings of the twenty-fourth international conference on architectural …, 2019
439*2019
A case for MLP-aware cache replacement
MK Qureshi, DN Lynch, O Mutlu, YN Patt
ACM SIGARCH Computer Architecture News 34 (2), 167-178, 2006
4302006
Adaptive insertion policies for managing shared caches
A Jaleel, W Hasenplaugh, M Qureshi, J Sebot, S Steely Jr, J Emer
Proceedings of the 17th international conference on Parallel architectures …, 2008
4232008
Accelerating critical section execution with asymmetric multi-core architectures
MA Suleman, O Mutlu, MK Qureshi, YN Patt
ACM SIGARCH Computer Architecture News 37 (1), 253-264, 2009
3952009
Improving read performance of phase change memories via write cancellation and write pausing
MK Qureshi, MM Franceschini, LA Lastras-Montano
HPCA-16 2010 The Sixteenth International Symposium on High-Performance …, 2010
3842010
Fundamental latency trade-off in architecting dram caches: Outperforming impractical sram-tags with a simple and practical design
MK Qureshi, GH Loh
2012 45th Annual IEEE/ACM International Symposium on Microarchitecture, 235-246, 2012
3582012
The V-Way cache: demand-based associativity via global replacement
MK Qureshi, D Thompson, YN Patt
32nd International Symposium on Computer Architecture (ISCA'05), 544-555, 2005
3272005
CEASER: Mitigating conflict-based cache attacks via encrypted-address and remapping
MK Qureshi
2018 51st Annual IEEE/ACM International Symposium on Microarchitecture …, 2018
3122018
Feedback-driven threading: power-efficient and high-performance execution of multi-threaded workloads on CMPs
MA Suleman, MK Qureshi, YN Patt
ACM Sigplan Notices 43 (3), 277-286, 2008
2852008
Low-cost inter-linked subarrays (LISA): Enabling fast inter-subarray data movement in DRAM
KK Chang, PJ Nair, D Lee, S Ghose, MK Qureshi, O Mutlu
2016 IEEE International Symposium on High Performance Computer Architecture …, 2016
2652016
AVATAR: A variable-retention-time (VRT) aware refresh for DRAM systems
MK Qureshi, DH Kim, S Khan, PJ Nair, O Mutlu
2015 45th Annual IEEE/IFIP International Conference on Dependable Systems …, 2015
2582015
Morphable memory system: A robust architecture for exploiting multi-level phase change memories
MK Qureshi, MM Franceschini, LA Lastras-Montaño, JP Karidis
ACM SIGARCH Computer Architecture News 38 (3), 153-162, 2010
2572010
ArchShield: Architectural framework for assisting DRAM scaling by tolerating high error rates
PJ Nair, DH Kim, MK Qureshi
ACM SIGARCH Computer Architecture News 41 (3), 72-83, 2013
2292013
NVRAM-aware logging in transaction systems
J Huang, K Schwan, MK Qureshi
Proceedings of the VLDB Endowment 8 (4), 389-400, 2014
2172014
PreSET: Improving performance of phase change memories by exploiting asymmetry in write times
MK Qureshi, MM Franceschini, A Jagmohan, LA Lastras
ACM SIGARCH Computer Architecture News 40 (3), 380-391, 2012
2112012
Cameo: A two-level memory organization with capacity of main memory and flexibility of hardware-managed cache
CC Chou, A Jaleel, MK Qureshi
2014 47th Annual IEEE/ACM International Symposium on Microarchitecture, 1-12, 2014
2062014
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