| A high-throughput and power-efficient FPGA implementation of YOLO CNN for object detection DT Nguyen, TN Nguyen, H Kim, HJ Lee IEEE Transactions on Very Large Scale Integration (VLSI) Systems 27 (8 …, 2019 | 442 | 2019 |
| Layer-specific optimization for mixed data flow with mixed precision in FPGA design for CNN-based object detectors DT Nguyen, H Kim, HJ Lee IEEE Transactions on Circuits and Systems for Video Technology 31 (6), 2450-2464, 2020 | 84 | 2020 |
| An approximate memory architecture for a reduction of refresh power consumption in deep learning applications DT Nguyen, H Kim, HJ Lee, IJ Chang 2018 IEEE International Symposium on Circuits and Systems (ISCAS), 1-5, 2018 | 81 | 2018 |
| An approximate memory architecture for energy saving in deep learning applications DT Nguyen, NH Hung, H Kim, HJ Lee IEEE Transactions on Circuits and Systems I: Regular Papers 67 (5), 1588-1601, 2020 | 62 | 2020 |
| ShortcutFusion: From Tensorflow to FPGA-based accelerator with reuse-aware memory allocation for shortcut data DT Nguyen, H Je, TN Nguyen, S Ryu, K Lee, HJ Lee IEEE Transaction on Circuits and Systems I: Regular Papers, 2022 | 28 | 2022 |
| Fast and Accurate Memory Simulation by Integrating DRAMSim2 into McSimA+ K Bick, DT Nguyen, HJ Lee, H Kim Electronics 7 (8), 152, 2018 | 7 | 2018 |
| An approximate DRAM with efficient refresh schemes for low power deep learning applications DT Nguyen, I Chang, HJ Lee, H Kim 2020 International Conference on Electronics, Information, and Communications, 2020 | 4 | 2020 |
| An Approximate DRAM design with an adjustable refresh scheme for low-power deep neural networks DT Nguyen, H Kim, HJ Lee Journal of Semiconductor Technology And Science 21 (2), 134-142, 2021 | 3 | 2021 |
| An adaptive row-based weight reuse scheme for FPGA implementation of convolutional neural networks H Je, DT Nguyen, K Lee, HJ Lee 2021 36th International Technical Conference on Circuits/Systems, Computers …, 2021 | 2 | 2021 |
| A fine-grained refresh scheme for a DRAM power reduction in deep learning application DT Nguyen, S Baek, H Kim IEIE Annual Summer Conference 2018, 2018 | 1 | 2018 |
| Approximate memory architecture and data processing apparatus having the same HJ Lee, H Kim, DT Nguyen, BY Kim, IJ Chang US Patent 10,916,291, 2021 | | 2021 |
| A multiplier-less quantization for a high performance YOLO-v2 implementation on FPGA DT Nguyen, TN Nguyen, H Kim, HJ Lee IEIE Annual Winter Conference 2019, 104-105, 2019 | | 2019 |
| 딥러닝 어플리케이션에서 리프레시 에너지 절감을 위한 비트 전치 유닛 기반의 근사 메모리 아키텍처 DT Nguyen, B Kim, H Kim, HJ Lee IEIE Annual Summer Conference 2019, 1502-1503, 2019 | | 2019 |
| 메모리 디바이스 및 그를 포함하는 데이터 처리 장치 김현， DT Nguyen， 김보열， 장익준， 이혁재 SK Patent 10-2019-0,062,777, 2019 | | 2019 |
| Bit Transpose Unit Design for Approximate Memory Architecture NH Hung, DT Nguyen, H Kim IEIE Annual Summer Conference 2018, 1600-1601, 2018 | | 2018 |
| QYOLO: A hardware design of quantized neural networks for low cost object detection TN Nguyen, DT Nguyen, H Kim IEIE Annual Summer Conference 2018, 2018 | | 2018 |
| A controller design for massive video data storage DT Nguyen, HJ Lee IEIE Annual Summer Conference 2014, 69-70, 2014 | | 2014 |
Hyun KimAssociate Professor, Seoul National University of Science and TechnologyBestätigte E-Mail-Adresse bei seoultech.ac.kr
