Curse of re-encryption: a generic power/EM analysis on post-quantum KEMs R Ueno, K Xagawa, Y Tanaka, A Ito, J Takahashi, N Homma
IACR Transactions on Cryptographic Hardware and Embedded Systems, 296-322, 2022
101 2022 Fault-injection attacks against NIST’s post-quantum cryptography round 3 KEM candidates K Xagawa, A Ito, R Ueno, J Takahashi, N Homma
Advances in Cryptology–ASIACRYPT 2021: 27th International Conference on the …, 2021
56 2021 Toward more efficient DPA-resistant AES hardware architecture based on threshold implementation R Ueno, N Homma, T Aoki
International Workshop on Constructive Side-Channel Analysis and Secure …, 2017
47 2017 Imbalanced data problems in deep learning-based side-channel attacks: Analysis and solution A Ito, K Saito, R Ueno, N Homma
IEEE Transactions on Information Forensics and Security 16, 3790-3802, 2021
44 2021 Highly Efficient R Ueno, N Homma, Y Sugawara, Y Nogami, T Aoki
Cryptographic Hardware and Embedded Systems--CHES 2015: 17th International …, 2015
44 2015 A High Throughput/Gate AES Hardware Architecture by Compressing Encryption and Decryption Datapaths: —Toward Efficient CBC-Mode Implementation R Ueno, S Morioka, N Homma, T Aoki
Cryptographic Hardware and Embedded Systems–CHES 2016: 18th International …, 2016
40 2016 High throughput/gate AES hardware architectures based on datapath compression R Ueno, S Morioka, N Miura, K Matsuda, M Nagata, S Bhasin, Y Mathieu, ...
IEEE Transactions on Computers 69 (4), 534-548, 2019
37 2019 Machine learning and hardware security: Challenges and opportunities F Regazzoni, S Bhasin, AA Pour, I Alshaer, F Aydin, A Aysu, V Beroulle, ...
Proceedings of the 39th International Conference on Computer-Aided Design, 1-6, 2020
32 2020 Multiple-valued plaintext-checking side-channel attacks on post-quantum kems Y Tanaka, R Ueno, K Xagawa, A Ito, J Takahashi, N Homma
IACR Transactions on Cryptographic Hardware and Embedded Systems 2023 (3 …, 2023
28 2023 On the success rate of side-channel attacks on masked implementations: information-theoretical bounds and their practical usage A Ito, R Ueno, N Homma
Proceedings of the 2022 ACM SIGSAC Conference on Computer and Communications …, 2022
27 2022 Bypassing isolated execution on risc-v using side-channel-assisted fault-injection and its countermeasure S Nashimoto, D Suzuki, R Ueno, N Homma
IACR Transactions on Cryptographic Hardware and Embedded Systems, 28-68, 2022
27 2022 Efficient fuzzy extractors based on ternary debiasing method for biased physically unclonable functions M Suzuki, R Ueno, N Homma, T Aoki
IEEE Transactions on Circuits and Systems I: Regular Papers 66 (2), 616-629, 2018
21 2018 Diffusional side-channel leakage from unrolled lightweight block ciphers: A case study of power analysis on PRINCE V Yli-Mäyry, R Ueno, N Miura, M Nagata, S Bhasin, Y Mathieu, T Graba, ...
IEEE Transactions on Information Forensics and Security 16, 1351-1364, 2020
19 2020 {SCARF}–A {Low-Latency} Block Cipher for Secure {Cache-Randomization} F Canale, T Güneysu, G Leander, JP Thoma, Y Todo, R Ueno
32nd USENIX Security Symposium (USENIX Security 23), 1937-1954, 2023
18 2023 Perceived information revisited: New metrics to evaluate success rate of side-channel attacks A Ito, R Ueno, N Homma
IACR Transactions on Cryptographic Hardware and Embedded Systems, 228-254, 2022
16 2022 Unified hardware for high-throughput AES-based authenticated encryptions S Sawataishi, R Ueno, N Homma
IEEE Transactions on Circuits and Systems II: Express Briefs 67 (9), 1604-1608, 2020
15 2020 Highly efficient R Ueno, N Homma, Y Nogami, T Aoki
Journal of Cryptographic Engineering 9, 101-113, 2019
13 2019 ELM: A low-latency and scalable memory encryption scheme A Inoue, K Minematsu, M Oda, R Ueno, N Homma
IEEE Transactions on Information Forensics and Security 17, 2628-2643, 2022
12 2022 Tackling biased PUFs through biased masking: A debiasing method for efficient fuzzy extractor R Ueno, M Suzuki, N Homma
IEEE Transactions on Computers 68 (7), 1091-1104, 2019
11 2019 A systematic design of tamper-resistant galois-field arithmetic circuits based on threshold implementation with (d+ 1) input shares R Ueno, N Homma, T Aoki
2017 IEEE 47th International Symposium on Multiple-Valued Logic (ISMVL), 136-141, 2017
11 2017 