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Sarma Vrudhula
Sarma Vrudhula
Sonstige NamenSarma Sastry, Sarma B.K. Vrudhula, S. Sastry
Arizona State University
Bestätigte E-Mail-Adresse bei asu.edu - Startseite
Titel
Zitiert von
Zitiert von
Jahr
Throughput-optimized OpenCL-based FPGA accelerator for large-scale convolutional neural networks
N Suda, V Chandra, G Dasika, A Mohanty, Y Ma, S Vrudhula, J Seo, ...
Proceedings of the 2016 ACM/SIGDA international symposium on field …, 2016
7282016
Battery modeling for energy aware system design
R Rao, S Vrudhula, DN Rakhmatov
Computer 36 (12), 77-87, 2003
6512003
Predictive modeling of the NBTI effect for reliable design
S Bhardwaj, W Wang, R Vattikonda, Y Cao, S Vrudhula
IEEE Custom Integrated Circuits Conference 2006, 189-192, 2006
5412006
Optimizing loop operation and dataflow in FPGA acceleration of deep convolutional neural networks
Y Ma, Y Cao, S Vrudhula, J Seo
Proceedings of the 2017 ACM/SIGDA International Symposium on Field …, 2017
4852017
An analytical high-level battery model for use in energy management of portable electronic systems
DN Rakhmatov, SBK Vrudhula
IEEE/ACM International Conference on Computer Aided Design. ICCAD 2001. IEEE …, 2001
4212001
Optimizing the convolution operation to accelerate deep neural networks on FPGA
Y Ma, Y Cao, S Vrudhula, J Seo
IEEE Transactions on Very Large Scale Integration (VLSI) Systems 26 (7 …, 2018
3842018
The impact of NBTI effect on combinational circuit: Modeling, simulation, and analysis
W Wang, S Yang, S Bhardwaj, S Vrudhula, F Liu, Y Cao
IEEE Transactions on Very Large Scale Integration (VLSI) Systems 18 (2), 173-183, 2009
3732009
Energy management for battery-powered embedded systems
D Rakhmatov, S Vrudhula
ACM Transactions on Embedded Computing Systems (TECS) 2 (3), 277-324, 2003
3572003
A model for battery lifetime analysis for organizing applications on a pocket computer
D Rakhmatov, S Vrudhula, DA Wallach
IEEE transactions on very large scale integration (VLSI) systems 11 (6 …, 2003
3302003
The impact of NBTI on the performance of combinational and sequential circuits
W Wang, S Yang, S Bhardwaj, R Vattikonda, S Vrudhula, F Liu, Y Cao
Proceedings of the 44th annual Design Automation Conference, 364-369, 2007
2962007
Mitigating effects of non-ideal synaptic device characteristics for on-chip learning
PY Chen, B Lin, IT Wang, TH Hou, J Ye, S Vrudhula, J Seo, Y Cao, S Yu
2015 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 194-199, 2015
2862015
Scalable and modularized RTL compilation of convolutional neural networks onto FPGA
Y Ma, N Suda, Y Cao, J Seo, S Vrudhula
2016 26th international conference on field programmable logic and …, 2016
2262016
Edge-valued binary decision for multi-level hierarchical verification
YT Lai, S Sastry
[1992] Proceedings 29th ACM/IEEE design automation conference, 608-613, 1992
2251992
BDD based decomposition of logic functions with application to FPGA synthesis
YT Lai, M Pedram, SBK Vrudhula
Proceedings of the 30th international Design Automation Conference, 642-647, 1993
2201993
Statistical timing analysis using bounds and selective enumeration
A Agarwal, D Blaauw, V Zolotov, S Vrudhula
Proceedings of the 8th ACM/IEEE international workshop on Timing issues in …, 2002
2082002
EPIMap: Using epimorphism to map applications on CGRAs
M Hamzeh, A Shrivastava, S Vrudhula
Proceedings of the 49th Annual Design Automation Conference, 1284-1291, 2012
1862012
EVBDD-based algorithms for integer linear programming, spectral transformation, and function decomposition
YT Lai, M Pedram, SBK Vrudhula
IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 1994
1851994
An automatic RTL compiler for high-throughput FPGA implementation of diverse deep convolutional neural networks
Y Ma, Y Cao, S Vrudhula, J Seo
2017 27th International Conference on Field Programmable Logic and …, 2017
1802017
Energy-efficient operation of multicore processors by DVFS, task migration, and active cooling
V Hanumaiah, S Vrudhula
IEEE Transactions on Computers 63 (2), 349-360, 2012
1572012
Fully parallel write/read in resistive synaptic array for accelerating on-chip learning
L Gao, IT Wang, PY Chen, S Vrudhula, J Seo, Y Cao, TH Hou, S Yu
Nanotechnology 26 (45), 455204, 2015
1562015
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