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Israel Koren
Israel Koren
Professor of Computer Engineering, University of Massachusetts
Bestätigte E-Mail-Adresse bei ecs.umass.edu - Startseite
Titel
Zitiert von
Zitiert von
Jahr
Computer arithmetic algorithms
I Koren
A.K. Peters, Ltd, 2002
2063*2002
Fault-tolerant systems
I Koren, CM Krishna
Morgan Kaufmann, 2020
14712020
Fault injection attacks on cryptographic devices: Theory, practice, and countermeasures
A Barenghi, L Breveglieri, I Koren, D Naccache
Proceedings of the IEEE 100 (11), 3056-3076, 2012
7382012
An introduction to cryptography
RA Mollin
Chapman and Hall/CRC, 2006
6232006
Error analysis and detection procedures for a hardware implementation of the advanced encryption standard
G Bertoni, L Breveglieri, I Koren, P Maistri, V Piuri
IEEE transactions on Computers 52 (4), 492-505, 2003
4512003
Defect tolerance in VLSI circuits: techniques and yield analysis
I Koren, Z Koren
Proceedings of the IEEE 86 (9), 1819-1838, 1998
3181998
Methods and apparatus for detecting defects in imaging arrays by image analysis
GH Chapman, I Koren, Z Koren, J Dudas, C Jung
US Patent 8,009,209, 2011
2642011
System-level power-aware design techniques in real-time systems
OS Unsal, I Koren
Proceedings of the IEEE 91 (7), 1055-1069, 2003
2522003
Complete and partial fault tolerance of feedforward neural nets
DS Phatak, I Koren
IEEE transactions on neural networks 6 (2), 446-456, 1995
2221995
A reconfigurable and fault-tolerant VLSI multiprocessor array
I Koren
Proceedings of the 8th annual symposium on Computer Architecture, 425-442, 1981
1761981
Fault tolerance in VLSI circuits
I Koren, AD Singh
Computer 23 (7), 73-83, 1990
1441990
Countermeasures against fault attacks on software implemented AES: effectiveness and cost
A Barenghi, L Breveglieri, I Koren, G Pelosi, F Regazzoni
Proceedings of the 5th Workshop on Embedded Systems Security, 1-10, 2010
1312010
Optimal aspect ratios of building blocks in VLSI
S Wimer, I Koren, I Cederbaum
IEEE transactions on computer-aided design of integrated circuits and …, 1989
1211989
Temperature aware floorplanning
Y Han, I Koren, CA Moritz
Workshop on Temperature Aware Computer Systems 24, 2005
1172005
Connectivity and performance tradeoffs in the cascade correlation learning architecture
DS Phatak, I Koren
IEEE Transactions on Neural Networks 5 (6), 930-935, 1994
1171994
Yield models for defect-tolerant VLSI circuits: A review
I Koren, CH Stapper
Defect and Fault Tolerance in VLSI Systems: Volume 1, 1-21, 1989
1171989
Evaluating elementary functions in a numerical coprocessor based on rational approximations
I Koren, O Zinaty
IEEE Transactions on Computers 39 (8), 1030-1037, 1990
1151990
Floorplans, planar graphs, and layouts
S Wimer, I Koren, I Cederbaum
IEEE Transactions on Circuits and Systems 35 (3), 267-278, 1988
1151988
Hybrid signed-digit number systems: A unified framework for redundant number representations with bounded carry propagation chains
DS Phatak, I Koren
IEEE Transactions on computers 43 (8), 880-891, 1994
1091994
A unified negative-binomial distribution for yield analysis of defect-tolerant circuits
I Koren, Z Koren, CH Stepper
IEEE Transactions on Computers 42 (6), 724-734, 2002
1082002
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