| TA-LRW: A replacement policy for error rate reduction in STT-MRAM caches E Cheshmikhani, H Farbeh, SG Miremadi, H Asadi IEEE Transactions on Computers 68 (3), 455-470, 2018 | 40 | 2018 |
| A System-Level Framework for Analytical and Empirical Reliability Exploration of STT-MRAM Caches E Cheshmikhani, H Farbeh, H Asadi IEEE Transactions on Reliability 69 (2), 594 - 610, 2020 | 27 | 2020 |
| Enhancing reliability of STT-MRAM caches by eliminating read disturbance accumulation E Cheshmikhani, H Farbeh, H Asadi 2019 Design, Automation & Test in Europe Conference & Exhibition (DATE), 854-859, 2019 | 25 | 2019 |
| A-CACHE: Alternating cache allocation to conduct higher endurance in NVM-based caches H Farbeh, AMH Monazzah, E Aliagha, E Cheshmikhani IEEE Transactions on Circuits and Systems II: Express Briefs 66 (7), 1237-1241, 2018 | 22 | 2018 |
| Investigating the effects of process variations and system workloads on reliability of STT-RAM caches E Cheshmikhani, AMH Monazzah, H Farbeh, SG Miremadi 2016 12th European Dependable Computing Conference (EDCC), 120-129, 2016 | 19 | 2016 |
| 3RSeT: Read Disturbance Rate Reduction in STT-MRAM Caches by Selective Tag Comparison E Cheshmikhani, H Farbeh, H Asadi IEEE Transactions on Computers 71 (6), 1305-1319, 2021 | 18 | 2021 |
| ROBIN: Incremental Oblique Interleaved ECC for Reliability Improvement in STT-MRAM Caches E Cheshmikhani, H Farbeh, H Asadi IEEE 24th Asia and South Pacific Design Automation Conference (ASP-DAC), 173-178, 2019 | 17 | 2019 |
| Probabilistic analysis of dynamic and temporal fault trees using accurate stochastic logic gates E Cheshmikhani, HR Zarandi Microelectronics Reliability 55 (11), 2468-2480, 2015 | 16 | 2015 |
| Fast fault tree analysis for hybrid uncertainties using stochastic logic implemented on field‐programmable gate arrays: An application in quantitative assessment and mitigation … S Shoar, HR Zarandi, F Nasirzadeh, E Cheshmikhani Quality and Reliability Engineering International 33 (7), 1367-1385, 2017 | 14 | 2017 |
| STAIR: HIGH RELIABLE STT-MRAM AWARE MULTI-LEVEL I/O CACHE ARCHITECTURE BY ADAPTIVE ECC ALLOCATION M Hadizadeh, E Cheshmikhani, H Asadi Design, Automation and Test in Europe Conference (DATE), 2020 | 11 | 2020 |
| CoPA: Cold page awakening to overcome retention failures in STT-MRAM based i/O buffers M Hadizadeh, E Cheshmikhani, M Rahmanpour, O Mutlu, H Asadi IEEE Transactions on Parallel and Distributed Systems 33 (10), 2304-2317, 2021 | 7 | 2021 |
| Accelerating accurate fault tree analysis using HW/SW co-design E Cheshmikhani, HR Zarandi, H Aliee 2014 Reliability and Maintainability Symposium, 1-6, 2014 | 5 | 2014 |
| IXIAM: ISA EXtension for Integrated Accelerator Management B Peccerillo, E Cheshmikhani, M Mannino, A Mondelli, S Bartolini IEEE Access 11, 33768-33791, 2023 | 4 | 2023 |
| A General Framework for Accelerator Management based on ISA Extension E Cheshmikhani, B Peccerillo, A Mondelli, S Bartolini IEEE Access, 2022 | 2 | 2022 |
| PREVENTING READ DISTURBANCE ACCUMULATION IN A CACHE MEMORY H Asadi, E Cheshmikhani, H Farbeh US Patent App. 16/798,451, 2020 | 1 | 2020 |
| Accelerating dynamic fault tree analysis based on stochastic logic utilizing GPGPUs E Cheshmikhani, HR Zarandi 2016 24th Euromicro International Conference on Parallel, Distributed, and …, 2016 | 1 | 2016 |
| Online Soft Error Tolerance in ReRAM Crossbars for Deep Learning Accelerators B Khezeli, HR Zarandi, E Cheshmikhani arXiv preprint arXiv:2412.03089, 2024 | | 2024 |
| A Low-Cost Fault-Tolerant Racetrack Cache Based on Data Compression E Cheshmikhani, F Shokouhinia, H Farbeh IEEE Transactions on Circuits and Systems II: Express Briefs, 2024 | | 2024 |
| Reducing Read Disturbance Error in Tag Array H Asadi, E Cheshmikhani US Patent US11430499 B2, 2022 | | 2022 |
| CoPA: Cold Page Awakening to Overcome Retention Failures in STT-MRAM Based I/O Buffers HA Mostafa Hadizadeh, Elham Cheshmikhani, Maysam Rahmanpour, Onur Mutlu arXiv e-prints, arXiv:2202.13409, 2022 | | 2022 |
Hamed FarbehAmirkabir University of TechnologyBestätigte E-Mail-Adresse bei aut.ac.ir