Hari Mohan Gaur, Ph.D

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Prof. Ashutosh Kumar SinghProfessor and Director, Indian Institute of Information Technology, Bhopal, IndiaBestätigte E-Mail-Adresse bei nitkkr.ac.in
UMESH GHANEKARNational Institute of Technology Kurukshetra, IndiaBestätigte E-Mail-Adresse bei nitkkr.ac.in
Dr. Trailokya Nath SasamalAssistant Professor, National Institute of TechnologyBestätigte E-Mail-Adresse bei nitkkr.ac.in
Vaibhav JainABES Institute of TechnologyBestätigte E-Mail-Adresse bei abesit.in
Devendra Kumar SharmaABES Engineering College, GhaziabadBestätigte E-Mail-Adresse bei abes.ac.in
Dhiraj K PradhanProfessor of Computer Science, University of BristolBestätigte E-Mail-Adresse bei cs.bris.ac.uk
Xiaoqing WenKyushu Institute of TechnologyBestätigte E-Mail-Adresse bei cse.kyutech.ac.jp
Masahiro FujitaUniversity of TokyoBestätigte E-Mail-Adresse bei ee.t.u-tokyo.ac.jp
Saptarshi GuptaSRM Institute of Science and TechnologyBestätigte E-Mail-Adresse bei srmist.edu.in
GAURAV SAININIT KurukshetraBestätigte E-Mail-Adresse bei nitkkr.ac.in
Vineet JaiswalPh.D. Scholar NIT Kurukshetra Haryana 136119Bestätigte E-Mail-Adresse bei nitkkr.ac.in
Valentina Emilia BalasProfessor, Aurel Vlaicu University of Arad / Academy of Romanian Scientists, ROMANIABestätigte E-Mail-Adresse bei uav.ro
Abhishek VermaBestätigte E-Mail-Adresse bei google.com
Vrijendra SinghProfessor, IT Dept.@Indian Institute of Information Technology AllahabadBestätigte E-Mail-Adresse bei iiita.ac.in
Jitendra KumarAssistant Professor, Maulana Azad National Institute of Technology BhopalBestätigte E-Mail-Adresse bei manit.ac.in
Prof. Anand MohanProfessor of Electronics Engineering, Indian Institute of Technology (BHU), VaranasiBestätigte E-Mail-Adresse bei itbhu.ac.in
Abhishek VermaAssistant Professor | Babasaheb Bhimrao Ambedkar University (A Central University) | PhD NIT-KKRBestätigte E-Mail-Adresse bei email.bbau.ac.in

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Hari Mohan Gaur, Ph.D

Goethe-Uni Frankfurt (Campus Riedberg), Germany

Bestätigte E-Mail-Adresse bei ieee.org

Reversible Logic Computer Architecture High-Performance Computing Quantum Circuits


Titel Nach Zitationen sortieren Nach Jahr sortieren Nach Titel sortieren	Zitiert von Zitiert von	Jahr
In-depth comparative analysis of reversible gates for designing logic circuits HM Gaur, AK Singh, U Ghanekar Procedia Computer Science 125, 810-817, 2018	44	2018
Design of reversible circuits with high testability HM Gaur, AK Singh Electronics Letters 52 (13), 1102-1104, 2016	42	2016
A review on online testability for reversible logic HM Gaur, AK Singh, U Ghanekar Procedia Computer Science 70, 384-391, 2015	40	2015
Testable design of reversible circuits using parity preserving gates HM Gaur, AK Singh, U Ghanekar IEEE Design & Test 35 (4), 56-64, 2017	29	2017
A new DFT methodology for k-CNOT reversible circuits and its implementation using quantum-dot cellular automata HM Gaur, AK Singh, U Ghanekar Optik 127 (22), 10593-10601, 2016	25	2016
Offline testing of reversible logic circuits: an analysis HM Gaur, AK Singh, U Ghanekar Integration 62, 50-67, 2018	23	2018
Design of reversible arithmetic logic unit with built-in testability HM Gaur, AK Singh, U Ghanekar IEEE Design & Test 36 (5), 54-61, 2019	21	2019
Computational analysis and comparison of reversible gates for design and test of logic circuits HM Gaur, AK Singh, A Mohan, DK Pradhan International Journal of Electronics 106 (11), 1679-1693, 2019	19	2019
Reversible logic: An introduction HM Gaur, TN Sasamal, AK Singh, A Mohan, DK Pradhan Design and Testing of Reversible Logic, 3-18, 2020	17	2020
Design for Stuck-at Fault Testability in MCT based Reversible Circuits UG HM Gaur, AK Singh Defence Science Journal 68 (4), 381-387, 2018	13*	2018
An efficient design of scalable reversible multiplier with testability HM Gaur, AK Singh, U Ghanekar Journal of Circuits, Systems and Computers 31 (10), 2250179, 2022	12	2022
Reversible circuit synthesis using evolutionary algorithms TN Sasamal, HM Gaur, AK Singh, A Mohan Design and Testing of Reversible Logic, 115-128, 2020	12	2020
Fault detection in multiple controlled Fredkin circuits AK Singh, HM Gaur, U Ghanekar IET Circuits, Devices & Systems 13 (5), 723-729, 2019	12	2019
Simplification and modification of multiple controlled Toffoli circuits for testability HM Gaur, AK Singh, U Ghanekar Journal of Computational Electronics 18, 356-363, 2019	12	2019
Reversible circuits with testability using quantum controlled NOT and swap gates HM Gaur, AK Singh, U Gaur Indian Journal of Pure & Applied Physics (IJPAP) 56 (7), 529-532, 2018	12	2018
Novel approaches for designing reversible counters TN Sasamal, HM Gaur, AK Singh, A Mohan Design and testing of reversible logic, 37-48, 2020	11	2020
Design for stuck-at fault testability in Toffoli–Fredkin reversible circuits HM Gaur, AK Singh, U Ghanekar National Academy Science Letters 44 (3), 215-220, 2021	9	2021
Area and energy optimized multilayer QCA-based 4N-bit scalable multiplier (M4N-MUL) V Jain, DK Sharma, HM Gaur The European Physical Journal Plus 137 (11), 1281, 2022	8	2022
Testable designs of toffoli fredkin reversible circuits HM Gaur, AK Singh, U Ghanekar arXiv preprint arXiv:2108.07448, 2021	8	2021
Comprehensive and Comparative Analysis of QCA based Circuit Designs for Next Generation Computation V Jain, DK Sharma, HM Gaur, AK Singh, X Wen ACM Computing Surveys, 2023	7	2023

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