| Prime: A novel processing-in-memory architecture for neural network computation in reram-based main memory P Chi, S Li, C Xu, T Zhang, J Zhao, Y Liu, Y Wang, Y Xie ACM SIGARCH Computer Architecture News 44 (3), 27-39, 2016 | 1863 | 2016 |
| Overcoming the challenges of crossbar resistive memory architectures C Xu, D Niu, N Muralimanohar, R Balasubramonian, T Zhang, S Yu, Y Xie 2015 IEEE 21st international symposium on high performance computer …, 2015 | 415 | 2015 |
| Nvmain 2.0: A user-friendly memory simulator to model (non-) volatile memory systems M Poremba, T Zhang, Y Xie IEEE Computer Architecture Letters 14 (2), 140-143, 2015 | 278 | 2015 |
| Sparse tensor core: Algorithm and hardware co-design for vector-wise sparse neural networks on modern gpus M Zhu, T Zhang, Z Gu, Y Xie Proceedings of the 52nd Annual IEEE/ACM International Symposium on …, 2019 | 172 | 2019 |
| Half-DRAM: A high-bandwidth and low-power DRAM architecture from the rethinking of fine-grained activation T Zhang, K Chen, C Xu, G Sun, T Wang, Y Xie ACM SIGARCH Computer Architecture News 42 (3), 349-360, 2014 | 161 | 2014 |
| Leap: a low energy assisted gps for trajectory-based services HS Ramos, T Zhang, J Liu, NB Priyantha, A Kansal Proceedings of the 13th international conference on Ubiquitous computing …, 2011 | 68 | 2011 |
| Eflops: Algorithm and system co-design for a high performance distributed training platform J Dong, Z Cao, T Zhang, J Ye, S Wang, F Feng, L Zhao, X Liu, L Song, ... 2020 IEEE International Symposium on High Performance Computer Architecture …, 2020 | 66 | 2020 |
| CREAM: A concurrent-refresh-aware DRAM memory architecture T Zhang, M Poremba, C Xu, G Sun, Y Xie 2014 IEEE 20th International Symposium on High Performance Computer …, 2014 | 58 | 2014 |
| Morphcache: A reconfigurable adaptive multi-level cache hierarchy S Srikantaiah, E Kultursay, T Zhang, M Kandemir, MJ Irwin, Y Xie 2011 IEEE 17th International Symposium on High Performance Computer …, 2011 | 52 | 2011 |
| A 3D SoC design for H. 264 application with on-chip DRAM stacking T Zhang, K Wang, Y Feng, Y Chen, Q Li, B Shao, J Xie, X Song, L Duan, ... 2010 IEEE International 3D Systems Integration Conference (3DIC), 1-6, 2010 | 41 | 2010 |
| Arithmetic unit design using 180nm TSV-based 3D stacking technology J Ouyang, G Sun, Y Chen, L Duan, T Zhang, Y Xie, MJ Irwin 2009 IEEE International Conference on 3D System Integration, 1-4, 2009 | 37 | 2009 |
| Thermomechanical stress-aware management for 3-D IC designs Q Zou, E Kursun, Y Xie IEEE Transactions on Very Large Scale Integration (VLSI) Systems 25 (9 …, 2017 | 36 | 2017 |
| Using multi-level cell STT-RAM for fast and energy-efficient local checkpointing P Chi, C Xu, T Zhang, X Dong, Y Xie 2014 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 301-308, 2014 | 32 | 2014 |
| A customized design of DRAM controller for on-chip 3D DRAM stacking T Zhang, K Wang, Y Feng, X Song, L Duan, Y Xie, X Cheng, YL Lin IEEE Custom Integrated Circuits Conference 2010, 1-4, 2010 | 32 | 2010 |
| RC-NVM: Enabling symmetric row and column memory accesses for in-memory databases P Wang, S Li, G Sun, X Wang, Y Chen, H Li, J Cong, N Xiao, T Zhang 2018 IEEE International Symposium on High Performance Computer Architecture …, 2018 | 25 | 2018 |
| 3D-SWIFT: A high-performance 3D-stacked wide IO DRAM T Zhang, C Xu, K Chen, G Sun, Y Xie Proceedings of the 24th Edition of the Great Lakes Symposium on VLSI, 51-56, 2014 | 24 | 2014 |
| RC-NVM: Dual-addressing non-volatile memory architecture supporting both row and column memory accesses S Li, N Xiao, P Wang, G Sun, X Wang, Y Chen, HH Li, J Cong, T Zhang IEEE Transactions on Computers 68 (2), 239-254, 2018 | 19 | 2018 |
| An efficient run-time encryption scheme for non-volatile main memory X Zhang, C Zhang, G Sun, J Di, T Zhang 2013 International conference on compilers, architecture and synthesis for …, 2013 | 17 | 2013 |
| Darb: A density-adaptive regular-block pruning for deep neural networks R Ao, Z Tao, W Yuhao, L Sheng, D Peiyan, C Yen-kuang, X Yuan, ... Proceedings of the AAAI Conference on Artificial Intelligence 34 (04), 5495-5502, 2020 | 16 | 2020 |
| Processing-in-memory in ReRAM-based main memory P Chi, S Li, C Xu, T Zhang, J Zhao, Y Wang, Y Liu, Y Xie SEAL-lab Technical Report 1, 2015, 2015 | 13 | 2015 |
Yuan XieChair Professor of Hong Kong University of Science and Technology (HKUST)Bestätigte E-Mail-Adresse bei ust.hk