| OuterSPACE: An Outer Product based Sparse Matrix Multiplication Accelerator S Pal, J Beaumont, DH Park, A Amarnath, S Feng, C Chakrabarti, HS Kim, ... 2018 IEEE International Symposium on High Performance Computer Architecture …, 2018 | 313 | 2018 |
| Sparse-TPU: Adapting Systolic Arrays for Sparse Matrices X He, S Pal, A Amarnath, S Feng, DH Park, A Rovinski, H Ye, Y Chen, ... Proceedings of the 34th ACM International Conference on Supercomputing, 1-12, 2020 | 99 | 2020 |
| A 7.3 M Output Non-Zeros/J, 11.7 M Output Non-Zeros/GB Reconfigurable Sparse Matrix–Matrix Multiplication Accelerator DH Park, S Pal, S Feng, P Gao, J Tan, A Rovinski, S Xie, C Zhao, ... IEEE Journal of Solid-State Circuits 55 (4), 933-944, 2020 | 34 | 2020 |
| Transmuter: Bridging the Efficiency Gap using Memory and Dataflow Reconfiguration S Pal, S Feng, D Park, S Kim, A Amarnath, CS Yang, X He, J Beaumont, ... Proceedings of the ACM International Conference on Parallel Architectures …, 2020 | 32 | 2020 |
| A 7.3 M Output Non-Zeros/J Sparse Matrix-Matrix Multiplication Accelerator using memory reconfiguration in 40 nm S Pal, D Park, S Feng, P Gao, J Tan, A Rovinski, S Xie, C Zhao, ... 2019 Symposium on VLSI Technology, C150-C151, 2019 | 27 | 2019 |
| CoSPARSE: A Software and Hardware Reconfigurable SpMV Framework for Graph Analytics S Feng, J Sun, S Pal, X He, K Kaszyk, D Park, M Morton, T Mudge, M Cole, ... 2021 58th ACM/IEEE Design Automation Conference (DAC), 949-954, 2021 | 24 | 2021 |
| SparseAdapt: Runtime Control for Sparse Linear Algebra on a Reconfigurable Accelerator S Pal, A Amarnath, S Feng, M O'Boyle, R Dreslinski, C Dubach MICRO-54: 54th Annual IEEE/ACM International Symposium on Microarchitecture …, 2021 | 20 | 2021 |
| Versa: A 36-Core Systolic Multiprocessor With Dynamically Reconfigurable Interconnect and Memory S Kim, M Fayazi, A Daftardar, KY Chen, J Tan, S Pal, T Ajayi, Y Xiong, ... IEEE Journal of Solid-State Circuits 57 (4), 986-998, 2022 | 18 | 2022 |
| STOMP: A Tool for Evaluation of Scheduling Policies in Heterogeneous Multi-Processors A Vega, A Amarnath, JD Wellman, H Kassa, S Pal, H Franke, ... arXiv preprint arXiv:2007.14371, 2020 | 16 | 2020 |
| Heterogeneity-Aware Scheduling on SoCs for Autonomous Vehicles A Amarnath, S Pal, HT Kassa, A Vega, A Buyuktosunoglu, H Franke, ... IEEE Computer Architecture Letters 20 (2), 82-85, 2021 | 14 | 2021 |
| Efficient Pruning for Machine Learning Under Homomorphic Encryption E Aharoni, M Baruch, P Bose, A Buyuktosunoglu, N Drucker, S Pal, ... European Symposium on Research in Computer Security, 204-225, 2023 | 13* | 2023 |
| Parallelism Analysis of Prominent Desktop Applications: An 18-year Perspective S Feng, S Pal, Y Yang, RG Dreslinski 2019 IEEE International Symposium on Performance Analysis of Systems and …, 2019 | 12 | 2019 |
| Accelerating Deep Neural Network Computation on a Low Power Reconfigurable Architecture Y Xiong, J Zhou, S Pal, D Blaauw, HS Kim, T Mudge, R Dreslinski, ... 2020 IEEE International Symposium on Circuits and Systems (ISCAS), 1-5, 2020 | 9 | 2020 |
| A Carbon Nanotube Transistor based RISC-V Processor using Pass Transistor Logic A Amarnath, S Feng, S Pal, T Ajayi, A Rovinski, RG Dreslinski 2017 IEEE/ACM International Symposium on Low Power Electronics and Design …, 2017 | 8 | 2017 |
| A New Design of an n-Bit Reversible Arithmetic Logic Unit S Pal, C Vudadha, PS Phaneendra, S Veeramachaneni, S Mandalika 2014 Fifth International Symposium on Electronic System Design, 224-225, 2014 | 8 | 2014 |
| STOMP: Agile Evaluation of Scheduling Policies in Heterogeneous Multi-Processors A Vega, JD Wellman, H Franke, A Buyuktosunoglu, P Bose, A Amarnath, ... DOSSA-3 Workshop@ HPCA, 2021 | 7 | 2021 |
| Accelerating Linear Algebra Kernels on a Massively Parallel Reconfigurable Architecture A Soorishetty, J Zhou, S Pal, D Blaauw, H Kim, T Mudge, R Dreslinski, ... ICASSP 2020-2020 IEEE International Conference on Acoustics, Speech and …, 2020 | 7 | 2020 |
| Branch target filtering based on memory region access count J Kalamatianos, A Yalavarti, V Agrawal, S Pal, V Srinivasan Lawrence Livermore National Laboratory (LLNL), Livermore, CA (United States …, 2023 | 6 | 2023 |
| Versa: A Dataflow-Centric Multiprocessor with 36 Systolic Arm Cortex-M4F Cores and a Reconfigurable Crossbar-Memory Hierarchy in 28nm S Kim, M Fayazi, A Daftardar, KY Chen, J Tan, S Pal, T Ajayi, Y Xiong, ... 2021 Symposium on VLSI Circuits, 1-2, 2021 | 6 | 2021 |
| OnSRAM: Efficient Inter-Node On-Chip Scratchpad Management in Deep Learning Accelerators S Pal, S Venkataramani, V Srinivasan, K Gopalakrishnan ACM Transactions on Embedded Computing Systems 21 (6), 1-29, 2022 | 5 | 2022 |
Ronald DreslinskiUniversity of MichiganBestätigte E-Mail-Adresse bei umich.edu