| Reducing power, leakage, and area of standard-cell asics using threshold logic flip-flops N Kulkarni, J Yang, JS Seo, S Vrudhula IEEE transactions on very large scale integration (VLSI) systems 24 (9 …, 2016 | 47 | 2016 |
| Integration of threshold logic gates with RRAM devices for energy efficient and robust operation J Yang, N Kulkarni, S Yu, S Vrudhula Proceedings of the 2014 IEEE/ACM International Symposium on Nanoscale …, 2014 | 20 | 2014 |
| Threshold logic in a flash A Wagle, G Singh, J Yang, S Khatri, S Vrudhula 2019 IEEE 37th International Conference on Computer Design (ICCD), 550-558, 2019 | 15 | 2019 |
| Design of threshold logic gates using emerging devices S Vrudhula, N Kulkami, J Yang 2015 IEEE International Symposium on Circuits and Systems (ISCAS), 373-376, 2015 | 15 | 2015 |
| Dynamic and leakage power reduction of ASICs using configurable threshold logic gates J Yang, J Davis, N Kulkarni, J Seo, S Vrudhula 2015 IEEE Custom Integrated Circuits Conference (CICC), 1-4, 2015 | 11 | 2015 |
| Threshold logic gates with resistive networks S Vrudhula, J Yang, N Kulkarni, S Yu US Patent 9,356,598, 2016 | 8 | 2016 |
| Digital IP protection using threshold voltage control J Davis, N Kulkarni, J Yang, A Dengi, S Vrudhula 2016 17th International Symposium on Quality Electronic Design (ISQED), 344-349, 2016 | 8 | 2016 |
| A fast, energy efficient, field programmable threshold-logic array N Kulkarni, J Yang, S Vrudhula 2014 International Conference on Field-Programmable Technology (FPT), 300-305, 2014 | 7 | 2014 |
| Energy efficient, robust differential mode d-flip-flop S Vrudhula, N Kulkarni, J Yang US Patent 10,250,236, 2019 | 6 | 2019 |
| Fast and robust differential flipflops and their extension to multi-input threshold gates J Yang, N Kulkarni, J Davis, S Vrudhula 2015 IEEE International Symposium on Circuits and Systems (ISCAS), 822-825, 2015 | 5 | 2015 |
| Non-volatile logic device for energy-efficient logic state restoration J Yang, S Vrudhula, A Dengi US Patent 10,795,809, 2020 | 4 | 2020 |
| Design considerations for energy-efficient and variation-tolerant nonvolatile logic J Yang, A Dengi, S Vrudhula IEEE Transactions on Very Large Scale Integration (VLSI) Systems 26 (12 …, 2018 | 4 | 2018 |
| FPGAs with reconfigurable threshold logic gates for improved performance, power and area A Wagle, J Yang, A Dengi, S Vrudhula 2018 28th International Conference on Field Programmable Logic and …, 2018 | 3 | 2018 |
| A New Approach to Clock Skewing for Area and Power Optimization of ASICs using Differential Flipflops and Local Clocking A Wagle, J Yang, N Kulkarni, S Vrudhula IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2023 | 1 | 2023 |
| Embedding Logic and Non-volatile Devices in CMOS Digital Circuits for Improving Energy Efficiency J Yang Arizona State University, 2018 | | 2018 |
