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Andreas Burg
Andreas Burg
EPFL - Telecommunications Circuits Laboratory
Bestätigte E-Mail-Adresse bei epfl.ch - Startseite
Titel
Zitiert von
Zitiert von
Jahr
VLSI implementation of MIMO detection using the sphere decoding algorithm
A Burg, M Borgmann, M Wenk, M Zellweger, W Fichtner, H Bolcskei
IEEE Journal of solid-state circuits 40 (7), 1566-1577, 2005
7722005
LLR-based successive cancellation list decoding of polar codes
A Balatsoukas-Stimming, MB Parizi, A Burg
IEEE transactions on signal processing 63 (19), 5165-5179, 2015
7632015
Soft-output sphere decoding: Algorithms and VLSI implementation
C Studer, A Burg, H Bolcskei
IEEE Journal on selected areas in Communications 26 (2), 290-300, 2008
4682008
MIMO transmission with residual transmit-RF impairments
C Studer, M Wenk, A Burg
2010 international ITG workshop on smart antennas (WSA), 189-196, 2010
3432010
Wireless communication and security issues for cyber–physical systems and the Internet-of-Things
A Burg, A Chattopadhyay, KY Lam
Proceedings of the IEEE 106 (1), 38-60, 2017
3072017
A low-complexity improved successive cancellation decoder for polar codes
O Afisiadis, A Balatsoukas-Stimming, A Burg
2014 48th Asilomar Conference on Signals, Systems and Computers, 2116-2120, 2014
2972014
K-best MIMO detection VLSI architectures achieving up to 424 Mbps
M Wenk, M Zellweger, A Burg, N Felber, W Fichtner
2006 IEEE International Symposium on Circuits and Systems, 4 pp.-1154, 2006
2142006
Prototype experience for MIMO BLAST over third-generation wireless system
A Adjoudani, EC Beck, AP Burg, GM Djuknic, TG Gvoth, D Haessig, ...
IEEE Journal on Selected Areas in Communications 21 (3), 440-451, 2003
1732003
Hardware architecture for list successive cancellation decoding of polar codes
A Balatsoukas-Stimming, AJ Raymond, WJ Gross, A Burg
IEEE Transactions on Circuits and Systems II: Express Briefs 61 (8), 609-613, 2014
1632014
Artificial intelligence for 5G and beyond 5G: Implementations, algorithms, and optimizations
C Zhang, YL Ueng, C Studer, A Burg
IEEE Journal on Emerging and Selected Topics in Circuits and Systems 10 (2 …, 2020
1542020
A fast and versatile quantum key distribution system with hardware key distillation and wavelength multiplexing
N Walenta, A Burg, D Caselunghe, J Constantin, N Gisin, O Guinnard, ...
New Journal of Physics 16 (1), 013047, 2014
1412014
An open-source LoRa physical layer prototype on GNU radio
J Tapparel, O Afisiadis, P Mayoraz, A Balatsoukas-Stimming, A Burg
2020 IEEE 21st International Workshop on Signal Processing Advances in …, 2020
1322020
LoRa digital receiver analysis and implementation
R Ghanaatian, O Afisiadis, M Cotting, A Burg
ICASSP 2019-2019 IEEE International Conference on Acoustics, Speech and …, 2019
1282019
On the error rate of the LoRa modulation with interference
O Afisiadis, M Cotting, A Burg, A Balatsoukas-Stimming
IEEE Transactions on Wireless Communications 19 (2), 1292-1304, 2019
1242019
VLSI implementation of a high-speed iterative sorted MMSE QR decomposition
P Luethi, A Burg, S Haene, D Perels, N Felber, W Fichtner
2007 IEEE International Symposium on Circuits and Systems, 1421-1424, 2007
1152007
Polarization-adjusted convolutional (PAC) codes: Sequential decoding vs list decoding
M Rowshan, A Burg, E Viterbo
IEEE Transactions on Vehicular Technology 70 (2), 1434-1447, 2021
114*2021
A successive cancellation decoder ASIC for a 1024-bit polar code in 180nm CMOS
A Mishra, AJ Raymond, LG Amaru, G Sarkis, C Leroux, P Meinerzhagen, ...
2012 IEEE Asian solid state circuits conference (A-SSCC), 205-208, 2012
1122012
VLSI design of approximate message passing for signal restoration and compressive sensing
P Maechler, C Studer, DE Bellasi, A Maleki, A Burg, N Felber, H Kaeslin, ...
IEEE Journal on Emerging and Selected Topics in Circuits and Systems 2 (3 …, 2012
1052012
Efficient ASIC implementation of a real-time depth mapping stereo vision system
M Kuhn, S Moser, O Isler, FK Gurkaynak, A Burg, N Felber, H Kaeslin, ...
2003 46th Midwest Symposium on Circuits and Systems 3, 1478-1481, 2003
992003
Benchmarking of Standard-Cell Based Memories in the Sub- Domain in 65-nm CMOS Technology
P Meinerzhagen, SMY Sherazi, A Burg, JN Rodrigues
IEEE Journal on Emerging and Selected Topics in Circuits and Systems 1 (2 …, 2011
982011
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