| Suppression of ambipolar behavior and simultaneous improvement in RF performance of gate-overlap tunnel field effect transistor (GOTFET) devices R Yadav, SS Dan, S Vidhyadharan, S Hariprasad Silicon 13, 1185-1197, 2021 | 18 | 2021 |
| A nanoscale gate overlap tunnel FET (GOTFET) based improved double tail dynamic comparator for ultra-low-power VLSI applications S Vidhyadharan, R Yadav, H Simhadri, SS Dan Analog Integrated Circuits and Signal Processing 101 (1), 109-117, 2019 | 16 | 2019 |
| Innovative multi-threshold gate-overlap tunnel FET (GOTFET) devices for superior ultra-low power digital, ternary and analog circuits at 45-nm technology node R Yadav, SS Dan, S Vidhyadharan, S Hariprasad Journal of Computational Electronics 19 (1), 291-303, 2020 | 14 | 2020 |
| A novel ultra-low-power gate overlap tunnel FET (GOTFET) dynamic adder S Vidhyadharan, SS Dan, R Yadav, S Hariprasad International Journal of Electronics 107 (10), 1663-1681, 2020 | 13 | 2020 |
| An advanced adiabatic logic using Gate Overlap Tunnel FET (GOTFET) devices for ultra-low power VLSI sensor applications S Vidhyadharan, R Yadav, S Hariprasad, SS Dan Analog Integrated Circuits and Signal Processing 102 (1), 111-123, 2020 | 12 | 2020 |
| Impact of the self-heating effect on nanosheet field effect transistor performance B Smaani, N Paras, SB Rahi, YS Song, R Yadav, S Tayal ECS Journal of Solid State Science and Technology 12 (2), 021005, 2023 | 11 | 2023 |
| Novel gate-overlap tunnel FET based innovative ultra-low-power ternary flash ADC S Vidhyadharan, SS Dan, SV Abhay, R Yadav, S Hariprasad Integration 73, 101-113, 2020 | 8 | 2020 |
| Part II: Benchmarking the Performance of Optimized TFET-Based Circuits with the Standard 45 nm CMOS Technology Using Device & Circuit Co-simulation Methodology S Vidhyadharan, Ramakant, G Akhilesh, V Gupta, A Ravi, SS Dan | 8 | 2019 |
| An efficient design approach for implementation of 2 bit ternary flash ADC using optimized complementary TFET devices S Vidhyadharan, R Ramakant, SV Abhay, AK Shyam, MP Hirpara, ... 2019 32nd International Conference on VLSI Design and 2019 18th …, 2019 | 7 | 2019 |
| An innovative ultra-low voltage GOTFET based regenerative-latch Schmitt trigger S Vidhyadharan, SS Dan, R Yadav, S Hariprasad Microelectronics Journal 104, 104879, 2020 | 6 | 2020 |
| Novel low and high threshold TFET based NTI and PTI cells benchmarked with standard 45 nm CMOS technology for ternary logic applications R Ramakant, S Vidhyadharan, AK Shyam, M Hirpara, T Chaudhary, ... 2019 32nd International Conference on VLSI Design and 2019 18th …, 2019 | 4 | 2019 |
| Compact modeling of junctionless gate-all-around MOSFET for circuit simulation: Scope and challenges B Smaani, F Nafa, AK Upadhyay, S Labiod, SB Rahi, MS Benlatreche, ... Device Circuit Co-Design Issues in FETs, 57-78, 2024 | 2 | 2024 |
| Low and High Vt GOTFET Devices Outperform Standard CMOS Technology in Ternary Logic Applications R Yadav, SS Dan, S Hariprasad IETE Technical Review 39 (5), 1114-1123, 2022 | 2 | 2022 |
| Double‐gate line‐tunneling field‐effect transistor devices for superior analog performance H Simhadri, SS Dan, R Yadav, A Mishra International Journal of Circuit Theory and Applications 49 (7), 2094-2111, 2021 | 2 | 2021 |
| Temperature Effect Assessment on the Gate-All-Around Junctionless FET for Bio-Sensing Applications B Smaani, S Labiod, MS Benlatreche, B Mehimmedetsi, R Yadav, ... International Journal of High Speed Electronics and Systems 33 (02n03), 2440061, 2024 | | 2024 |
| Mathematical Approach for a Future Semiconductor Roadmap SB Rahi, AK Upadhyay, YS Song, N Sahni, R Yadav, UC Bind, G Naima, ... Negative Capacitance Field Effect Transistors, 114-126, 2023 | | 2023 |
| Analysis and Reduction of GOTFET Capacitances Using Physics-Based Compact Modeling R Yadav, SS Dan, RM Vemuri International Symposium on VLSI Design and Test, 119-134, 2023 | | 2023 |
| Novel gate-overlap tunnel FETs for superior analog, digital, and ternary logic circuit applications S Hariprasad, R Yadav, SS Dan Device Circuit Co-Design Issues in FETs, 79-122, 2023 | | 2023 |
| Mathematical Approach for the Foundation of Negative Capacitance Technology SB Rahi, AK Upadhyay, YS Song, N Sahni, R Yadav, UC Bind, G Naima, ... Negative Capacitance Field Effect Transistors 1, 11, 2023 | | 2023 |
| Part I: Optimization of the Tunnel FET Device Structure for Achieving Circuit Performance Better Than the Current Standard 45 nm CMOS Technology SP Physics | | 2019 |
Sanjay VidhyadharanVisiting Faculty, EEE Dept. BITS Pilani Hyderabad CampusBestätigte E-Mail-Adresse bei hyderabad.bits-pilani.ac.in
