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Pramod Kumar Meher
Pramod Kumar Meher
C. V. Raman Global University, Bhubaneswar, India
Bestätigte E-Mail-Adresse bei sandhaanlabs.in
Titel
Zitiert von
Zitiert von
Jahr
50 years of CORDIC: Algorithms, architectures, and applications
PK Meher, J Valls, TB Juang, K Sridharan, K Maharatna
IEEE Transactions on Circuits and Systems I: Regular Papers 56 (9), 1893-1907, 2009
7282009
FPGA realization of FIR filters by efficient and flexible systolization using distributed arithmetic
PK Meher, S Chandrasekaran, A Amira
IEEE transactions on signal processing 56 (7), 3009-3017, 2008
3472008
Efficient integer DCT architectures for HEVC
PK Meher, SY Park, BK Mohanty, KS Lim, C Yeo
IEEE Transactions on Circuits and systems for Video Technology 24 (1), 168-178, 2013
2422013
Efficient FPGA and ASIC realizations of a DA-based reconfigurable FIR digital filter
SY Park, PK Meher
IEEE Transactions on Circuits and Systems II: Express Briefs 61 (7), 511-515, 2014
2232014
New approach to look-up-table design and memory-based realization of FIR digital filter
PK Meher
IEEE Transactions on Circuits and Systems I: Regular Papers 57 (3), 592-603, 2009
2042009
A high-performance energy-efficient architecture for FIR adaptive filter based on new distributed arithmetic formulation of block LMS algorithm
BK Mohanty, PK Meher
IEEE transactions on signal processing 61 (4), 921-932, 2012
1512012
Low-power, high-throughput, and low-area adaptive FIR filter based on distributed arithmetic
SY Park, PK Meher
IEEE Transactions on Circuits and Systems II: Express Briefs 60 (6), 346-350, 2013
1452013
A high-performance FIR filter architecture for fixed and reconfigurable applications
BK Mohanty, PK Meher
IEEE transactions on very large scale integration (VLSI) systems 24 (2), 444-452, 2015
1342015
FPGA implementation of orthogonal matching pursuit for compressive sensing reconstruction
H Rabah, A Amira, BK Mohanty, S Almaadeed, PK Meher
IEEE Transactions on very large scale integration (VLSI) Systems 23 (10 …, 2014
1342014
Nonlinear channel equalization for wireless communication systems using Legendre neural networks
JC Patra, PK Meher, G Chakraborty
Signal Processing 89 (11), 2251-2262, 2009
1272009
Hardware-efficient systolization of DA-based calculation of finite digital convolution
PK Meher
IEEE Transactions on Circuits and Systems II: Express Briefs 53 (8), 707-711, 2006
1262006
Critical-path analysis and low-complexity implementation of the LMS adaptive algorithm
PK Meher, SY Park
IEEE Transactions on Circuits and Systems I: Regular Papers 61 (3), 778-788, 2013
1062013
Efficient CORDIC algorithms and architectures for low area and high throughput implementation
L Vachhani, K Sridharan, PK Meher
IEEE Transactions on Circuits and Systems II: Express Briefs 56 (1), 61-65, 2009
1062009
Memory efficient modular VLSI architecture for highthroughput and low-latency implementation of multilevel lifting 2-D DWT
BK Mohanty, PK Meher
IEEE Transactions on Signal processing 59 (5), 2072-2084, 2011
1022011
Memory-Efficient High-Speed Convolution-based Generic Structure for Multilevel 2-D DWT
BK Mohanty, PK Meher
IEEE Transactions on Circuits and Systems for Video Technology 23 (2), 353-363, 2013
952013
Legendre-FLANN-based nonlinear channel equalization in wireless communication system
JC Patra, WC Chin, PK Meher, G Chakraborty
2008 IEEE international conference on systems, man and cybernetics, 1826-1831, 2008
932008
Systolic and Super-Systolic Multipliers for Finite Field Based on Irreducible Trinomials
PK Meher
IEEE Transactions on Circuits and Systems I: Regular Papers 55 (4), 1031-1040, 2008
922008
An optimized lookup-table for the evaluation of sigmoid function for artificial neural networks
PK Meher
2010 18th IEEE/IFIP International Conference on VLSI and System-on-Chip, 91-95, 2010
902010
High-throughput pipelined realization of adaptive FIR filter based on distributed arithmetic
PK Meher, SY Park
2011 IEEE/IFIP 19th International Conference on VLSI and System-on-Chip, 428-433, 2011
892011
Area-delay-power efficient fixed-point LMS adaptive filter with low adaptation-delay
PK Meher, SY Park
IEEE Transactions on Very Large Scale Integration (VLSI) Systems 22 (2), 362-371, 2013
872013
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