| Product code schemes for error correction in MLC NAND flash memories C Yang, Y Emre, C Chakrabarti IEEE Transactions on Very Large Scale Integration (VLSI) Systems 20 (12 …, 2011 | 125 | 2011 |
| Enhancing the reliability of STT-RAM through circuit and system level techniques Y Emre, C Yang, K Sutaria, Y Cao, C Chakrabarti 2012 IEEE Workshop on Signal Processing Systems, 125-130, 2012 | 49 | 2012 |
| Compact modeling of STT-MTJ devices Z Xu, C Yang, M Mao, KB Sutaria, C Chakrabarti, Y Cao Solid-State Electronics 102, 76-81, 2014 | 35 | 2014 |
| Improving reliability of non-volatile memory technologies through circuit level techniques and error control coding C Yang, Y Emre, Y Cao, C Chakrabarti EURASIP Journal on Advances in Signal Processing 2012, 1-24, 2012 | 33 | 2012 |
| Hierarchical modeling of phase change memory for reliable design Z Xu, KB Sutaria, C Yang, C Chakrabarti, Y Cao 2012 IEEE 30th International Conference on Computer Design (ICCD), 115-120, 2012 | 19 | 2012 |
| Compact modeling of STT-MTJ for SPICE simulation Z Xu, KB Sutaria, C Yang, C Chakrabarti, Y Cao 2013 Proceedings of the European Solid-State Device Research Conference …, 2013 | 18 | 2013 |
| Multi-tiered approach to improving the reliability of multi-level cell PRAM C Yang, Y Emre, Y Cao, C Chakrabarti 2012 IEEE Workshop on Signal Processing Systems, 114-119, 2012 | 18 | 2012 |
| Data storage time sensitive ECC schemes for MLC NAND flash memories C Yang, D Muckatira, A Kulkarni, C Chakrabarti 2013 IEEE International Conference on Acoustics, Speech and Signal …, 2013 | 14 | 2013 |
| Flexible product code-based ECC schemes for MLC NAND flash memories C Yang, Y Emre, C Chakrabarti, T Mudge 2011 IEEE Workshop on Signal Processing Systems (SiPS), 255-260, 2011 | 11 | 2011 |
| Cost-effective design solutions for enhancing pram reliability and performance C Yang, M Mao, Y Cao, C Chakrabarti IEEE Transactions on Multi-Scale Computing Systems 3 (1), 1-11, 2016 | 10 | 2016 |
| A low cost multi-tiered approach to improving the reliability of multi-level cell PRAM C Yang, Y Emre, Z Xu, H Chen, Y Cao, C Chakrabarti Journal of Signal Processing Systems 76, 133-147, 2014 | 8 | 2014 |
| Improving the reliability of MLC NAND flash memories through adaptive data refresh and error control coding C Yang, HM Chen, TN Mudge, C Chakrabarti Journal of Signal Processing Systems 76, 225-234, 2014 | 6 | 2014 |
| SPICE modeling of STT-RAM for resilient design Z Xu, K Sutaria, C Yang, C Chakrabarti, Y Cao Proc. 5th Int. MOS-AK/GSA Workshop, 2012 | 3 | 2012 |
| Low cost ECC schemes for improving the reliability of DRAM+ PRAMMAIN memory systems M Mao, C Yang, Z Xu, Y Cao, C Chakrabarti 2014 IEEE Workshop on Signal Processing Systems (SiPS), 1-6, 2014 | 2 | 2014 |
| 19 Heterogeneous Memory Design C Yang, Z Xu, C Chakrabarti, Y Cao VLSI: Circuits for Emerging Applications 1 (10), 407, 2014 | | 2014 |
| Improving the Reliability of NAND Flash, Phase-change RAM and Spin-torque Transfer RAM C Yang Arizona State University, 2014 | | 2014 |
| Compact Modeling of STT Compact Modeling of STT-MTJ Compact Modeling of STT Compact Modeling of STT-MTJ Compact Modeling of STT Compact Modeling of STT MTJ for SPICE Simulation Z Xu, K Sutaria, C Yang, C Chakrabarti, YK Cao | | |
Chaitali ChakrabartiProfessor of Electrical Engineering, SECEE, Arizona State UniversityBestätigte E-Mail-Adresse bei asu.edu
