| Reliability simulation for analog ICs: Goals, solutions, and challenges A Toro-Frías, P Martín-Lloret, J Martín-Martínez, R Castro-López, E Roca, ... Integration 55, 341-348, 2016 | 38 | 2016 |
| CASE: A reliability simulation tool for analog ICs P Martín-Lloret, A Toro-Frías, R Castro-López, E Roca, FV Fernández, ... 2017 14th International Conference on Synthesis, Modeling, Analysis and …, 2017 | 18 | 2017 |
| An automated layout-aware design flow A Toro-Frias, R Castro-Lopez, E Roca, FV Fernández 2012 International Conference on Synthesis, Modeling, Analysis and …, 2012 | 12 | 2012 |
| A model parameter extraction methodology including time-dependent variability for circuit reliability simulation J Diaz-Fortuny, P Saraza-Canflanca, A Toro-Frías, R Castro-López, ... 2018 15th International Conference on Synthesis, Modeling, Analysis and …, 2018 | 11 | 2018 |
| A size-adaptive time-step algorithm for accurate simulation of aging in analog ICs P Martín-Lloret, A Toro-Frías, J Martín-Martínez, R Castro-López, E Roca, ... 2017 IEEE International Symposium on Circuits and Systems (ISCAS), 1-4, 2017 | 10 | 2017 |
| Design considerations of an SRAM array for the statistical validation of time-dependent variability models P Saraza-Canflanca, D Malagon, F Passos, A Toro, J Núñez, ... 2018 15th International Conference on Synthesis, Modeling, Analysis and …, 2018 | 8 | 2018 |
| Including a stochastic model of aging in a reliability simulation flow A Toro-Frías, P Martín-Lloret, R Castro-López, E Roca, FV Fernández, ... 2017 14th International Conference on Synthesis, Modeling, Analysis and …, 2017 | 7 | 2017 |
| Layout-aware pareto fronts of electronic circuits A Toro-Frías, R Castro-López, E Roca, FV Fernández 2011 20th European Conference on Circuit Theory and Design (ECCTD), 345-348, 2011 | 6 | 2011 |
| A fast and accurate reliability simulation method for analog circuits A Toro-Frias, R Castro-López, E Roca, FV Fernández, J Martin-Martinez, ... 2015 International Conference on Synthesis, Modeling, Analysis and …, 2015 | 5 | 2015 |
| Lifetime calculation using a stochastic reliability simulator for analog ICs A Toro-Frías, P Martín-Lloret, J Martinez, R Castro-López, E Roca, ... 2018 15th International Conference on Synthesis, Modeling, Analysis and …, 2018 | 4 | 2018 |
| Circuit reliability prediction: challenges and solutions for the device time-dependent variability characterization roadblock M Nafria, J Diaz-Fortuny, P Saraza-Canflanca, J Martín-Martínez, E Roca, ... 2021 IEEE Latin America Electron Devices Conference (LAEDC), 1-4, 2021 | 3 | 2021 |
| Generation of Lifetime-Aware Pareto-Optimal Fronts Using a Stochastic Reliability Simulator A Toro-Frías, P Saraza-Canflanca, F Passos, P Martín-Lloret, ... 2019 Design, Automation & Test in Europe Conference & Exhibition (DATE), 78-83, 2019 | 3 | 2019 |
| Automated massive RTN characterization using a transistor array chip P Saraza, J Diaz-Fortuny, A Toro-Frías, R Castro-López, E Roca, ... 2018 15th International Conference on Synthesis, Modeling, Analysis and …, 2018 | 2 | 2018 |
| Modeling of variability and reliability in analog circuits J Martin-Martinez, J Diaz-Fortuny, A Toro-Frias, P Martin-Lloret, ... | | 2020 |
| Diseño de circuitos analógicos y de señal mixta con consideraciones de diseño físico y variabilidad A Toro Frías | | 2017 |